Overvoltage Protection in Stacked SOI IC Chips

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Solution Overview

Problem

Integrated circuit chips with very thin SOI layers face damage from overvoltages due to the inability to integrate protection components within the layer, necessitating the use of bulkier external discrete components, which increases cost and assembly complexity.

Innovation Solution

Incorporating protection components, such as bipolar transistors or Shockley diodes, within the thicker SOI layer of an optoelectronic chip to protect electronic components on thinner SOI layers, utilizing an interposer plate for direct chip-to-chip mounting and connecting these components across terminals of both chips to manage differential overvoltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protection components are integrated in the thin SOI layer with electronic components, then protection against overvoltages is achieved, but the protection components are damaged or destroyed by overvoltage currents

Engineering Contradiction:
Improveovervoltage protectionVSAvoidcomponent durability
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent moves the protection components from the thin SOI layer (2D plane) to a third dimension by using a thicker SOI layer in a separate optoelectronic chip. This dimensional transition allows protection components to be physically separated from the electronic components they protect, enabling them to withstand overvoltage currents without damage while still providing protection through electrical connection via the interposer plate.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If discrete external protection components are used, then protection against overvoltages is achieved, but bulk and assembly cost increase

Engineering Contradiction:
Improveovervoltage protectionVSAvoidassembly complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the protection components with the optoelectronic chip by integrating them into the same thicker SOI layer. This combination eliminates the need for separate discrete external protection components, reducing assembly complexity and bulk while maintaining overvoltage protection functionality through the integrated structure and interposer plate connection.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for effective overvoltage protection within the thin SOI layer without damaging the components, reducing bulk and assembly costs by integrating protection components in the thicker SOI layer, enabling efficient protection against electrostatic discharges.

Implementation Method 1

Chip 3 comprises a silicon substrate 10 coated with a silicon oxide layer 11, itself coated with an SOI layer 12

Methodology Applied
Scientific EffectSOI (Silicon on Insulator) layer structure:

Implementation Method 2

Interconnection structures 8 of chips 1 and 2 are arranged opposite to interconnection structures 13 of chip 3

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9453977B2Assembly of integrated circuit chips having an overvoltage protection component
Publication Date: 2016.09.27 STMICROELECTRONICS INT NV
  • US9453977B2 patent drawing
  • US9453977B2 patent drawing
  • US9453977B2 patent drawing

AI summary

A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.