SOI High-Bandwidth Circuitry Charge Layer Elimination
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Solution Overview
Problem
High-resistivity silicon substrates used in RF applications can form a charge layer at the handle wafer/oxide interface, leading to high loss, low isolation, and low linearity due to parasitic conduction layers, which existing solutions like trap-rich layers or expensive substrate changes fail to address effectively in standard manufacturing environments.
Innovation Solution
The integration of trench lattice structures and ion impurity implants in high-resistivity silicon substrates eliminates the charge layer by positioning trench structures between active circuits and under passive structures, using a buried oxide layer to fill the trenches and reduce harmonic distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-resistivity silicon substrates are used in RF applications, then substrate loss is reduced and isolation is improved, but a charge layer forms at the handle wafer/oxide interface causing high loss and low linearity
Solution Approach 1:
The substrate surface is segmented by forming an array of trenches that divide the continuous charge layer into isolated regions. These trenches are filled with dielectric material to create discrete isolation structures that prevent the formation of a continuous parasitic conduction layer while maintaining high substrate isolation.
Solution Approach 2:
Dielectric material is introduced as an intermediary substance to fill the trenches and prevent direct contact between the handle wafer and the active circuit regions. This intermediary layer blocks the formation of the charge layer at critical interfaces while allowing the high-resistivity substrate to maintain its isolation properties.
2Reliability
If trap-rich layers or shield layers are added to reduce charge layer effects, then harmonic distortion is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The invention changes the physical parameters of the substrate structure by introducing trenches with specific dimensions and spacing. By controlling trench depth, width, and fill material properties, the charge layer formation is suppressed through parameter optimization rather than adding complex layers, maintaining compatibility with standard manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates the charge layer, enhancing substrate resistance and linearity, suitable for high-speed applications like power amplifiers and RF circuits without the need for expensive alternatives, improving manufacturing feasibility.
Implementation Method 1
an ion impurity implant
Implementation Method 2
buried oxide (BOX) layer is positioned on and contacts the HRS substrate layer
Data Source
AI summary
A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.