SOI Substrate Cleavage and Bonding Without Implantation Defects
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Solution Overview
Problem
Conventional semiconductor-on-insulator (SOI) substrate manufacturing processes face challenges in minimizing defects and contamination from implantation processes, which can affect the quality of the SOI substrate and devices formed on it, particularly due to the use of sacrificial layers and implantation species.
Innovation Solution
The method involves forming a wafer structure with a buffer layer and semiconductor cap, defining a cleavage plane through implantation, removing the sacrificial layer, and bonding the dielectric layers to create a SOI substrate, thereby avoiding implantation-related defects and contamination, and using a dielectric-to-dielectric bonding interface for improved substrate quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If implantation process is used to define cleavage plane, then cleavage plane can be defined, but defects and contamination are introduced
Solution Approach 1:
The patent removes the implantation process entirely from the cleavage plane definition method. Instead of using implantation species to define the cleavage plane, the invention uses a sacrificial layer that is selectively removed through chemical etching, thereby extracting the harmful implantation step while preserving the functional outcome of cleavage plane definition.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary material between the buffer layer and the semiconductor cap. This sacrificial layer serves as a mediator that defines the cleavage plane through its selective removal, replacing the direct implantation approach and avoiding the introduction of defects and contamination associated with implantation species.
2Manufacturing precision
If sacrificial layer is used, then cleavage plane can be defined, but additional process steps and potential contamination are introduced
Solution Approach 1:
The patent combines the sacrificial layer formation with the existing buffer layer structure. The sacrificial layer is integrated into the wafer structure during the buffer layer formation process, merging multiple functions into a single integrated approach that reduces overall process complexity while maintaining cleavage plane definition capability.
3Productivity
If conventional SOI substrate manufacturing is used, then SOI substrate can be produced, but implantation-related defects affect substrate quality
Solution Approach 1:
The patent converts the harmful effect of implantation by replacing it with a chemical etching process. The sacrificial layer is designed to be selectively removable through chemical etching, transforming the harmful implantation approach into a beneficial chemical process that defines the cleavage plane without introducing defects or contamination, thereby improving substrate quality while maintaining production capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes defects and contamination, enhances the quality of the SOI substrate, and allows for the reuse of substrates, reducing fabrication costs and improving device performance by avoiding implantation-induced issues and using a high-quality dielectric interface.
Implementation Method 1
performing an implantation process to implant implantation species through the sacrificial layer into the buffer layer, so as to define a cleavage plane in the buffer layer
Implementation Method 2
bonding the dielectric layers to each other to form a bonded wafer structure
Implementation Method 3
performing a splitting process to separate the bonded wafer structure along the cleavage plane
Data Source
AI summary
A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.