Adaptive Hysteresis Control for SOI Clock Signals
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Solution Overview
Problem
Hysteresis effects in Silicon on Insulator (SOI) technology lead to increased latency and power consumption in data processing circuits, necessitating excessive guard-bands and degrading performance in source synchronous bus channels.
Innovation Solution
Adaptive hysteresis control circuitry is implemented, using counters to track elapsed time and characterize hysteresis parameters, such as the number of cycles to attain a typical duty cycle and dead-time, to mitigate hysteresis effects in clock signals, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard-band is added to cover hysteresis-related effects, then reliability is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by pre-characterizing hysteresis parameters during silicon testing and storing them in lookup tables. During runtime, the system retrieves pre-computed correction values based on the characterized parameters, avoiding the need to add excessive guard-bands while maintaining reliability. This eliminates the trade-off between reliability and latency by having solutions prepared in advance.
2Reliability
If guard-band is added to cover hysteresis-related effects, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent uses preliminary characterization of hysteresis effects during manufacturing testing, storing the results in lookup tables. During operation, the system retrieves pre-computed correction values rather than adding excessive guard-bands, thereby maintaining reliability while avoiding the continuous power consumption that would result from always operating with conservative timing margins.
3Productivity
If hysteresis mitigation is implemented using adaptive control, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by creating lookup tables that store pre-characterized hysteresis correction values from silicon testing. Instead of implementing complex real-time hysteresis compensation algorithms, the system copies pre-computed values from lookup tables based on measured parameters, achieving productivity improvement through simple table lookup operations rather than complex computational logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adaptive hysteresis control circuitry effectively reduces hysteresis-related latency and power consumption, enhancing data processing circuit performance by dynamically managing hysteresis based on pre-characterized parameters, improving the efficiency of data propagation in SOI technology.
Implementation Method 1
Hysteresis is due to a memory effect where the previous switching activity influences the threshold voltage of the SOI transistor in a subsequent switching activity
Data Source
AI summary
Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.