SOI CMOS Doped Layer Isolation for Leakage Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in reducing leakage current, particularly between NMOS and PMOS regions, due to the lack of effective isolation between doped layers, which affects the performance and density of semiconductor devices.
Innovation Solution
A semiconductor device is designed with doped layers in NMOS and PMOS regions on a silicon-on-insulator substrate, where an element isolation layer completely separates the doped layers, reducing leakage current by forming a distinct separation between the NMOS and PMOS regions using an element isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped layers in NMOS and PMOS regions are not completely separated, then device density can be maintained, but leakage current occurs between regions
Solution Approach 1:
An element isolation layer is introduced as an intermediary structure between the NMOS and PMOS doped layers. This isolation layer completely separates the doped layers, preventing leakage current while maintaining a relatively simple overall device structure. The isolation layer acts as a mediator that resolves the conflict between electrical isolation and structural simplicity.
2Reliability
If gate length is increased to improve current control, then current control capability improves, but device density decreases
Solution Approach 1:
The patent transitions from controlling current primarily through gate length (one-dimensional control) to utilizing vertical isolation structures (element isolation layer) that operate in a different dimensional approach. This allows effective current control between NMOS and PMOS regions without requiring increased gate length, thereby maintaining high device density while improving current control capability.
Data Source
AI summary
A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.