SOI CMOS Logic Gate Redundancy for SET Mitigation
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Solution Overview
Problem
Advanced semiconductor processes make integrated circuits more sensitive to Single Event Transients (SETs) and Single Event Upsets (SEUs) due to reduced node capacitance and lower operating voltages, leading to errors and incorrect operations.
Innovation Solution
The implementation of a redundant logic output system in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits, where a primary logic output is duplicated and combined with an interleaved C-gate to emulate an inverter output only when both match, thereby mitigating radiation-induced errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced semiconductor processes with smaller feature sizes are used, then electrical performance is improved, IC area is reduced, and power consumption is decreased, but sensitivity to SETs and SEUs increases
Solution Approach 1:
The patent implements redundancy by duplicating logic gates and their interconnections. Each primary logic gate is paired with a redundant copy, and the system uses voting mechanisms to detect and correct errors caused by radiation events, thereby maintaining reliability despite increased sensitivity to SETs and SEUs
Solution Approach 2:
The patent changes the operational parameters by using different voltage levels and timing schemes in the redundant logic paths. By varying these parameters between primary and redundant circuits, the system can distinguish between legitimate signal variations and radiation-induced errors, reducing false error detection while maintaining protection against actual SETs and SEUs
2Reliability
If redundant logic gates and interleaved C-gates are implemented, then mitigation of SETs and SEUs is achieved, but device complexity increases
Solution Approach 1:
The patent segments the logic circuit into primary and redundant sections with distinct functional blocks. By dividing the circuit architecture into modular segments that can be independently analyzed and tested, the system achieves comprehensive error mitigation while organizing the complexity in a manageable and systematic manner
Solution Approach 2:
The patent introduces C-gates as intermediary elements between primary and redundant logic gates. These C-gates serve as mediators that monitor the outputs of both primary and redundant paths and coordinate the voting decision, thereby simplifying the overall control logic and reducing the complexity of error detection and correction mechanisms
Data Source
AI summary
A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.