SOI Semiconductor Contact Resistance Reduction via Segmented Metal Silicide

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Solution Overview

Problem

Existing methods for forming metal silicide layers in semiconductor structures with thin source/drain regions, such as ultra-thin SOI or finFET, lead to silicon depletion and short-circuits due to increased contact resistance, which impairs device performance.

Innovation Solution

A method involving the deposition and removal of thin first and second metal layers, followed by the formation of amorphous semiconductor layers, which are then annealed to form thin contact layers, effectively reducing contact resistance while preventing silicon depletion and short-circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal layers are deposited on surfaces of source/drain regions to form metal silicide layers, then contact resistance is reduced, but silicon in source/drain regions is depleted completely leading to short-circuits

Engineering Contradiction:
Improvecontact resistanceVSAvoidsilicon depletion
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The contact layer is divided into multiple segments: a first contact layer (metal silicide) and a second contact layer (different material). This segmentation allows each layer to perform its function optimally - the first layer provides low contact resistance while the second layer prevents further silicon depletion and short-circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first contact layer acts as an intermediary between the metal layer and the source/drain region. It facilitates electrical contact while the second contact layer serves as a protective intermediary that prevents direct excessive interaction between the metal and silicon, avoiding complete silicon depletion.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of substance

If raised source/drain regions are formed by epitaxial growing to increase thickness, then silicon depletion is prevented, but distance between contact layers and channels increases hindering device performance

Engineering Contradiction:
Improvesilicon depletion preventionVSAvoiddistance from channel
Core Design Contradiction:
Loss of substanceVSLength of moving object

Solution Approach 1:

Instead of changing the geometric parameter (thickness) of the source/drain region through epitaxial growth, the invention changes the material composition parameter by introducing a multi-layer contact structure. This maintains the original source/drain thickness (short distance to channel) while preventing silicon depletion through the protective second contact layer.

Inventive Principle:
Principle #35Parameter changes

3Loss of substance

If self-limited process is used to deposit and remove metal layers, then thin metal silicide layers are formed preventing silicon depletion, but lateral electrical resistance is great impairing device performance

Engineering Contradiction:
Improvesilicon depletion preventionVSAvoidlateral electrical resistance
Core Design Contradiction:
Loss of substanceVSReliability

Solution Approach 1:

The contact structure uses composite materials - combining a metal silicide layer (first contact layer) with a different material layer (second contact layer). The metal silicide provides low lateral electrical resistance while the second material layer prevents silicon depletion, achieving both requirements simultaneously through material composition rather than relying solely on thin layer geometry.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces contact resistance at source/drain regions while maintaining semiconductor performance by forming thin contact layers within the amorphous semiconductor layers, thereby preventing silicon depletion and short-circuits.

Implementation Method 1

metal layers are deposited on surfaces of source/drain regions, then the semiconductor structure is annealed such that the metal layers react with source/drain regions to form metal silicide layers

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

annealing the semiconductor structure

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS9209269B2Semiconductor structure and method for manufacturing the same
Publication Date: 2015.12.08 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US9209269B2 patent drawing
  • US9209269B2 patent drawing
  • US9209269B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.