SOI Current Mirror Circuit for Temperature-Stable Reference Current
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Solution Overview
Problem
Existing semiconductor circuits require precise and constant reference voltages and resistors to maintain a stable reference current over temperature variations, which can be costly and complex to implement.
Innovation Solution
A circuit design utilizing fully depleted SOI transistors in current mirror configurations with self-biased back gate contacts to generate a CTAT current, combining it with a PTAT current to produce a reference current or voltage that remains relatively constant over a wide temperature range, avoiding the need for precise resistors and additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If bipolar devices and additional manufacturing steps are used to generate stable reference current over temperature, then temperature stability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the temperature compensation function from complex bipolar devices and implements it using simple CMOS transistors in a current mirror configuration. The core invention uses only four CMOS transistors (M1-M4) to generate both PTAT and CTAT currents, eliminating the need for bipolar devices and reducing manufacturing steps while maintaining temperature stability.
Solution Approach 2:
The patent changes the operating parameters by using CMOS transistors in saturation mode with specific current mirror ratios to generate temperature-compensated reference current. By adjusting the transistor dimensions and bias conditions, the circuit achieves temperature independence without requiring precise resistors or additional manufacturing processes.
2Stability of the object's composition
If precise resistors and constant reference voltages are used to maintain stable reference current, then current stability is improved, but circuit complexity and component requirements increase
Solution Approach 1:
The patent implements a self-biasing mechanism where the CMOS transistor current mirror automatically generates the required PTAT and CTAT currents based on its own operating conditions. The circuit uses the inherent properties of MOS transistors in saturation mode to create temperature compensation, eliminating the need for external precise resistors and reference voltage sources.
Solution Approach 2:
The patent merges the functions of multiple separate components (resistors, reference voltage sources, bipolar devices) into a single integrated CMOS current mirror circuit. The four transistors work together to simultaneously generate PTAT current through M1-M2 and CTAT current through M3-M4, which are then combined to produce the temperature-stable reference current.
3Temperature
If bipolar devices are used to generate temperature-stable reference current, then temperature range coverage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces expensive, precision-critical bipolar devices with standard CMOS transistors that have adequate process variation margins. The current mirror configuration is inherently robust to transistor parameter variations, allowing the use of standard-cell CMOS processes without requiring tight manufacturing tolerances or precision resistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable reference current or voltage with reduced manufacturing complexity and cost, maintaining accuracy across varying temperatures without relying on bipolar devices or complex threshold voltage altering techniques.
Implementation Method 1
a back gate contact of the first SOI transistor is connected to a gate of the first SOI transistor, a gate of the second SOI transistor, and a drain of the second SOI transistor
Data Source
AI summary
A CTAT circuit that generates a CTAT current. The circuit includes two SOI transistors of a first conductivity type arranged in a current mirror configuration where the gates of the two transistors and the back gate contact of one of the transistors is connected to the drain of the other transistor. The SOI transistor of the first conductivity type whose back gate contact is connected to the drain of the other SOI transistor of the first conductivity type is located in current path that carries a CTAT current. In some embodiments, the drains of the two transistors are each coupled to a drain of a respective one of a second pair of SOI transistors of a second conductivity type, where the second pair of SOI transistors are also configured in a current mirror configuration.