SOI Device Source Drain Height Variation
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Solution Overview
Problem
In semiconductor devices, particularly those of the SOI type, the miniaturization leads to increased parasitic capacitances due to raised source/drain regions, which affect the gate-drain capacitance and resistance, making it challenging to maintain low resistance while reducing parasitic capacitances.
Innovation Solution
The semiconductor device features source and drain regions with different height levels, where the drain region is formed in direct contact with the base substrate and the source region is on the semiconductor film, and a method involving forming a gate structure over an SOI substrate, recessing the substrate to create a trench for the drain region, and epitaxially growing source and drain regions with varying heights to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain regions are raised to reduce resistance, then electrical conductivity improves, but parasitic capacitance increases
Solution Approach 1:
The patent applies different height levels to different regions: the source region is raised to reduce contact resistance, while the drain region remains at the base substrate level to minimize parasitic capacitance. This local differentiation allows each region to be optimized for its specific function without compromising the other.
Solution Approach 2:
The source and drain regions are segmented into different height levels rather than being uniform. The source region is elevated above the base substrate while the drain region stays at the base level, creating distinct functional zones that address different electrical requirements simultaneously.
2Productivity
If device dimensions are miniaturized to increase integration density, then productivity improves, but parasitic capacitance increases
Solution Approach 1:
Within the miniaturized device structure, the drain region is kept at the base substrate level while the source region is raised, creating local structural variation that reduces parasitic capacitance without increasing overall device footprint, thereby maintaining high integration density.
3Reliability
If source region is raised above base substrate, then contact resistance decreases, but device complexity increases
Solution Approach 1:
Only the source region is raised above the base substrate while the drain region remains at the base level, creating a localized structural modification rather than a comprehensive redesign. This minimizes the increase in device complexity while achieving the goal of reduced contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the gate-drain capacitance while maintaining low resistance in the source/drain contacts, effectively addressing the challenge of high parasitic capacitances in miniaturized SOI devices.
Implementation Method 1
epitaxially growing source and drain regions with varying heights to reduce parasitic capacitance
Data Source
AI summary
The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.