SOI Die Support Structures for Etched Non-Rectangular Singulation

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Solution Overview

Problem

Conventional semiconductor package manufacturing methods using sawing techniques result in chipping and cracking of semiconductor dies, limiting the production of non-rectangular shapes and compromising package reliability.

Innovation Solution

Employing etching techniques to form notches in semiconductor wafers, followed by the application of mold compounds and singulation methods to create silicon-on-insulator (SOI) dies with reduced warpage and enhanced support structures, allowing for various die shapes and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sawing techniques are used to separate semiconductor dies, then productivity is improved through batch processing, but manufacturing precision deteriorates due to chipping and cracking of dies

Engineering Contradiction:
Improvebatch processing efficiencyVSAvoiddie integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the semiconductor wafer processing into distinct stages: first forming notches in the wafer to define individual die boundaries, then applying mold compound to protect the die, and finally separating the dies. This segmentation allows the use of gentle etching processes instead of forceful sawing, eliminating chipping and cracking while maintaining batch processing efficiency through the use of wafer-level operations before singulation.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional sawing methods are used for die separation, then ease of manufacture is maintained through simple equipment, but reliability deteriorates due to mechanical stress and damage to the die

Engineering Contradiction:
Improveprocess simplicityVSAvoidpackage reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an intermediary substance (mold compound) that is applied to the semiconductor die before separation. This mold compound acts as a protective intermediary that prevents mechanical damage during the separation process. The etching process also serves as an intermediary method that gradually separates the die without the sudden mechanical stress of sawing, thereby maintaining reliability while preserving manufacturing simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If rectangular die shapes are produced using conventional methods, then manufacturing precision is maintained through straightforward cutting, but adaptability deteriorates by limiting non-rectangular shapes

Engineering Contradiction:
Improvecutting accuracyVSAvoiddie shape variety
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent changes the fundamental parameter of the separation process from mechanical cutting to chemical etching. This parameter change enables the formation of various die shapes (non-rectangular) by controlling the etching pattern, while still achieving high precision through the protective mold compound and controlled etching conditions. The etching process can be programmed to create different geometries without sacrificing accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260018417A1Silicon-on-insulator die support structures and related methods
Publication Date: 2026.01.15 SEMICON COMPONENTS IND LLC
  • US20260018417A1 patent drawing
  • US20260018417A1 patent drawing
  • US20260018417A1 patent drawing

AI summary

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.