SOI Die Support Structures for Non-Rectangular Wafer Separation
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Solution Overview
Problem
Conventional semiconductor package manufacturing methods using sawing techniques result in chipping and cracking of semiconductor dies, limiting the production of non-rectangular shapes and compromising package reliability.
Innovation Solution
Employing etching techniques to form notches in semiconductor wafers, followed by the application of mold compounds and singulation methods to create silicon-on-insulator (SOI) dies with improved structural integrity and shape flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sawing techniques are used to separate semiconductor dies, then productivity is improved through efficient wafer separation, but manufacturing precision deteriorates due to chipping and cracking of dies
Solution Approach 1:
The patent replaces the mechanical sawing system with a chemical etching system. Instead of using physical saw blades to separate dies, the invention uses chemical etchants to selectively remove material along predefined separation lines, eliminating mechanical contact that causes chipping and cracking while maintaining efficient wafer separation
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element between the die structure and the separation process. This sacrificial layer is selectively removed through etching to create separation channels, allowing dies to be separated without direct mechanical interaction, thus preventing damage while maintaining productivity
2Ease of manufacture
If conventional sawing methods are used, then ease of manufacture is maintained through simple processing, but reliability deteriorates due to chipping and cracking
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer and defining etch paths before the actual separation process. This pre-preparation allows subsequent chemical etching to proceed smoothly without complex mechanical operations, maintaining ease of manufacture while eliminating chipping and cracking that compromise reliability
Solution Approach 2:
The invention substitutes mechanical sawing with chemical etching processes. The chemical method removes material through controlled reactions rather than mechanical force, simplifying the separation process while eliminating the chipping and cracking that occur with mechanical contact, thereby improving reliability without sacrificing ease of manufacture
3Manufacturing precision
If rectangular die shapes are produced through conventional methods, then manufacturing precision is maintained for standard geometries, but adaptability deteriorates by limiting non-rectangular shapes
Solution Approach 1:
The patent employs parameter changes by modifying the etch pattern parameters defined in the sacrificial layer. By changing the geometric parameters of the etch paths (curves, angles, variable widths), the process can produce diverse die shapes including non-rectangular geometries while maintaining manufacturing precision through controlled chemical etching
Solution Approach 2:
The invention applies local quality by allowing different regions of the wafer to have different etch patterns and removal rates. The chemical etching process can be selectively applied to specific areas with different geometries, enabling production of various die shapes (rectangular, circular, irregular) across the same wafer while maintaining high geometric accuracy through localized process control
Data Source
AI summary
Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.