SOI Substrate Diode Topography Tolerant Contact Structure
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Solution Overview
Problem
The fabrication of sophisticated SOI semiconductor devices faces challenges in forming substrate diodes due to significant yield losses and performance degradation caused by the pronounced surface topography and reduced heat dissipation, leading to unreliable temperature sensing and potential leakage paths in the metallization layer.
Innovation Solution
The semiconductor devices are designed with a reconfigured substrate diode area where metal lines are electrically connected exclusively to one type of diode electrodes, avoiding leakage paths by maintaining a lateral distance from the other type of electrodes, and using local interconnects and contact trenches to connect diode electrodes within the contact level, thus reducing the impact of surface topography on electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If substrate diodes are formed in the crystalline substrate material below the buried insulating layer, then temperature sensing capability is improved, but surface topography becomes pronounced causing manufacturing issues
Solution Approach 1:
The patent transitions from planar substrate diode formation to three-dimensional contact structures that extend through the buried insulating layer. Contact trenches are formed vertically through the insulating layer to reach the substrate diodes, enabling temperature sensing functionality while maintaining a planar upper surface for subsequent manufacturing processes.
Solution Approach 2:
The patent segments the contact structure into multiple components: contact openings in the first interlayer insulating film, contact trenches through the second interlayer insulating layer, and separate metal lines for anode and cathode connections. This segmentation allows independent optimization of each component to resolve the topography conflict.
2Area of stationary object
If metal lines are positioned close to both anode and cathode regions, then device area is reduced, but leakage paths may form between opposite polarity regions
Solution Approach 1:
The patent segments the metal interconnect system into separate metal lines for anode and cathode connections. First metal lines contact only anode regions through contact elements, while second metal lines contact only cathode regions through contact trenches. This segmentation eliminates the risk of leakage paths between opposite polarity regions while maintaining compact device layout.
Solution Approach 2:
The patent introduces insulating layers (first and second interlayer insulating films) as intermediary materials between metal lines and diode electrodes. These insulating layers provide electrical isolation and allow metal lines to be positioned close to both anode and cathode regions without direct contact, preventing leakage paths while minimizing device area.
3Ease of manufacture
If conventional contact structures are used with pronounced surface topography, then additional process steps are required, but manufacturing complexity increases
Solution Approach 1:
The patent designs contact trenches and metal line structures that serve multiple functions: providing electrical connection to substrate diodes, enabling temperature sensing, preventing leakage paths, and maintaining compatibility with subsequent planar manufacturing processes. This multi-functionality reduces the need for additional specialized process steps.
Solution Approach 2:
The patent performs preliminary formation of contact trenches and insulation layers before depositing metal lines. This preliminary action creates a prepared substrate that accommodates metal line deposition without requiring additional planarization steps, simplifying the overall manufacturing process while handling the topography issue.
Data Source
AI summary
In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided.


