SOI Structure with Graded Dopant Profile for Harmonic Suppression
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Solution Overview
Problem
Conventional silicon-on-insulator (SOI) substrates used in RF switches often generate second and third order harmonics beyond FCC limits due to fixed charges in the insulator layer or at the interface between the insulator and silicon substrate, leading to impedance variations with input signals.
Innovation Solution
A silicon-on-insulator structure with a semiconductor substrate having a first portion with a lower dopant concentration and a second portion with a higher dopant concentration, optionally including micro-cavities, to increase resistivity and suppress parasitic inversion charge formation, thereby reducing harmonic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional SOI substrate is used, then the structure is simple and manufacturing is easy, but second and third order harmonics are generated beyond FCC limits
Solution Approach 1:
The patent applies local quality by creating a non-uniform dopant concentration distribution within the semiconductor substrate. Specifically, a higher dopant concentration is introduced in a first region (near the insulator interface) compared to a second region (deeper in the substrate). This localized variation in dopant concentration allows the structure to suppress parasitic inversion charge formation at the critical interface region while maintaining overall substrate functionality, thereby reducing harmonic generation without requiring complete structural redesign
Solution Approach 2:
The patent employs parameter changes by modifying the dopant concentration parameter within the semiconductor substrate. By adjusting the dopant concentration from a first value in the first region to a second value in the second region, the electrical characteristics of the substrate are optimized. This parameter modification changes the threshold voltage of parasitic capacitors and suppresses inversion charge formation, effectively reducing harmonic generation while maintaining manufacturing feasibility through standard doping processes
2Stability of the object's composition
If fixed charge is present in the insulator layer or at the interface, then the conventional SOI structure is maintained, but inversion charge forms at the top surface leading to impedance variations
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the semiconductor substrate with a specific dopant concentration profile before the insulator layer is formed or before device operation begins. The higher dopant concentration in the first region creates a preliminary electrical condition that counteracts the harmful effect of fixed charges in the insulator layer. This preemptive doping strategy suppresses inversion charge formation at the interface before it can occur during device operation, thereby preventing impedance variations while maintaining the conventional SOI structural composition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively minimizes harmonic generation by raising the threshold voltage of parasitic capacitors, reducing harmonic behavior while maintaining high resistivity and minimizing additional manufacturing costs.
Implementation Method 1
The second portion can extend from the first portion up to the second surface and can comprise, in a second concentration that is greater than the first concentration, any of the following: the same dopant as in the first portion, a different dopant than that in the first portion but with the same conductivity type, or a combination thereof
Implementation Method 2
Optionally, the second portion can also comprise a plurality of micro-cavities so as to balance out, within the second portion, a dopant induced increase in conductivity with a corresponding micro-cavity induced increase in resistivity
Data Source
AI summary
Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.