SOI Substrate Doped Pattern Formation via Segmented Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing semiconductor-on-insulator (SOI) substrates with doped regions face challenges such as dopant contamination and variability due to ion implantation, leading to random dopant fluctuation and threshold voltage variability, which complicates circuit optimization and limits the formation of buried circuitry.
Innovation Solution
A method involving the formation of doped regions and alignment marks within the handle substrate prior to bonding with a donor substrate, using ion implantation and thermal annealing, which suppresses the formation of dopant tails and allows for precise control of dopant profiles and dimensions, thereby enhancing bonding quality and reducing resist edge ion implantation deflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ions are implanted through the top semiconductor layer and buried dielectric layer to create doped areas in the carrier substrate, then doped patterns can be formed for buried circuitry, but dopant tails contaminate the top semiconductor layer causing random dopant fluctuation and threshold voltage variability
Solution Approach 1:
The patent divides the substrate into separate functional layers: a carrier substrate for mechanical support and doped pattern formation, a buried dielectric layer for isolation, and a top semiconductor layer for device fabrication. By forming doped patterns in the carrier substrate before bonding, the dopant confinement is segmented from the top semiconductor layer, preventing contamination while maintaining manufacturing capability.
Solution Approach 2:
The buried dielectric layer serves as an intermediary barrier between the doped carrier substrate and the top semiconductor layer. This intermediate layer physically separates the dopant source from the sensitive channel region, allowing doped patterns to be formed in the carrier substrate without dopant tails migrating into and contaminating the top semiconductor layer.
2Quantity of substance
If high dose ion implantation is performed to achieve desired dopant levels, then doped patterns can be formed, but thermal annealing is required which causes dopant diffusion and makes it difficult to obtain precise dopant levels
Solution Approach 1:
The doped patterns are formed in the carrier substrate before bonding to the top semiconductor layer. This preliminary action allows the dopant to be implanted and activated in the carrier substrate without subsequent thermal processing that would cause diffusion into the top layer, enabling precise dopant level control while achieving the required dopant concentration.
Solution Approach 2:
The patent applies different processing conditions to different regions: the carrier substrate receives high dose ion implantation for creating doped patterns with specific dopant concentrations, while the top semiconductor layer is protected from such processing. This local differentiation allows high dopant concentrations to be achieved in the carrier substrate without causing contamination in the top layer.
3Reliability
If the active dopant level at the interface between carrier substrate and buried dielectric is increased to improve buried circuitry performance, then circuit functionality is enhanced, but dopant contamination of the top semiconductor layer increases causing threshold voltage variability
Solution Approach 1:
The buried dielectric layer acts as an intermediary barrier that allows high dopant concentrations to be maintained at the carrier substrate-dielectric interface for improved buried circuitry performance, while simultaneously preventing dopant migration into the top semiconductor layer. This intermediary structure decouples the dopant concentration requirements of buried circuitry from the purity requirements of the top layer devices.
Solution Approach 2:
The patent segments the dopant distribution into distinct regions: high dopant concentration in the carrier substrate for buried circuitry functionality, zero dopant concentration in the top semiconductor layer for device performance. This segmentation is achieved through separate formation of doped patterns in the carrier substrate before bonding, preventing dopant contamination while maintaining buried circuitry performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor substrates with precise dopant profiles and dimensions, reducing threshold voltage variability and enabling more reproducible and compact integrated circuits by preventing dopant contamination and tail formation.
Implementation Method 1
forming a pattern of one or more doped regions inside the handle substrate by at least one ion implantation step for implanting the dopant
Implementation Method 2
it has been proposed to implant through the top semiconductor layer and the buried dielectric layer deeply into the carrier substrate. This method, however, requires thermal annealing steps that are essential to diffuse the dopant upward toward the interface between the carrier substrate and the buried dielectric
Data Source
AI summary
The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.