SOI Device Charge Sinking via Doped Substrate Regions
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Solution Overview
Problem
Semiconductor devices fabricated using silicon-on-insulator technologies face performance drops during high current drive operations due to charge accumulation in the substrate at the interface with the buried oxide layer, which affects the signal-to-noise ratio and device output current.
Innovation Solution
The implementation of trench isolation regions surrounding an active device region on a silicon-on-insulator wafer, along with a doped region in the substrate adjacent to the trench isolation regions and the buried oxide layer, helps to minimize charge accumulation by providing a path for charge dissipation, ensuring the doped region and well have the same conductivity type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a BFMOAT is formed in the substrate to minimize substrate coupling and improve signal-to-noise ratio, then substrate coupling is minimized and signal-to-noise ratio is improved, but charge accumulates in the substrate at and near the interface with the buried oxide layer during high current drive operation, causing device output current to drop
Solution Approach 1:
A doped region is introduced as an intermediary charge sink between the BFMOAT and the buried oxide layer. This doped region provides a controlled path for charge dissipation, mediating the conflict between maintaining low substrate coupling and preventing charge accumulation that causes current drops during high current drive operation
Solution Approach 2:
The substrate region is modified by introducing a doped region with altered electrical properties (different conductivity type or doping concentration) compared to the surrounding BFMOAT region. This parameter change creates a localized charge sink that actively manages charge accumulation while preserving the overall low-coupling characteristics of the BFMOAT
2Productivity
If the doped region is positioned adjacent to the trench isolation regions and buried oxide layer, then charge dissipation path is optimized and current drops are reduced, but device structure complexity increases
Solution Approach 1:
The doped region is merged with the existing trench isolation structure, utilizing the same fabrication processes and spatial arrangement. This integration combines the isolation function with the charge sink function, reducing overall device complexity while achieving effective charge management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces or eliminates current drops associated with charge accumulation, enhancing the signal-to-noise ratio and maintaining device performance during high current drive operations.
Implementation Method 1
a doped region arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type
Data Source
AI summary
Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.