SOI DRAM SRAM Logic IC Back Gate Biasing
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Solution Overview
Problem
Silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) faces limitations in providing back bias flexibility due to a grounded N+ substrate, which restricts the adjustment of threshold voltage in transistors with back gates.
Innovation Solution
The fabrication of integrated circuits with field effect transistors (FETs) that include a unitary N+ layer below the buried oxide (BOX) layer, a P-type region acting as a back gate, and logic/static RAM FETs, where the N+ layer functions as a plate electrode of a trench capacitor, allowing for independent electrical biasing of the P and N+ back gates to adjust the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a grounded N+ substrate is used in SOI technology with eDRAM, then the substrate provides structural support and electrical grounding, but the threshold voltage adjustment flexibility is restricted due to inability to independently bias the back gate
Solution Approach 1:
The substrate structure is segmented into distinct functional layers: a grounded N+ substrate layer and a separate P-type back gate layer. This segmentation allows independent electrical biasing of the back gate while maintaining the structural and grounding functions of the N+ substrate, thereby resolving the contradiction between adaptability and device complexity.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the N+ substrate and the P-type back gate region. This buffer layer enables independent electrical control of the back gate while maintaining proper electrical isolation and structural integrity, allowing threshold voltage adjustment without compromising substrate grounding.
2Reliability
If thin silicon and BOX layers are used to enable fully depleted device operation with back gate control, then short channel effects are reduced and threshold variability is minimized, but junction leakage increases
Solution Approach 1:
The invention optimizes the doping concentration and thickness parameters of the P-type back gate region and the buffer layer to achieve a balance between minimizing junction leakage and maintaining effective back gate control. By carefully controlling these parameters, the structure reduces short channel effects while suppressing junction leakage through optimized electrical fields.
Data Source
AI summary
An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.