SOI DRAM Cell Layout With Buried Bit Lines for Higher Density
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Solution Overview
Problem
Current Dynamic Random Access Memory (DRAM) technologies face limitations in integration density and control ability due to larger cell configuration sizes and buried type bit line structures.
Innovation Solution
A semiconductor structure and manufacturing method utilizing a Silicon On Insulator (SOI) substrate with buried type bit lines and intersecting word lines, eliminating the need for line contact holes and reducing unit configuration size, thereby enhancing control ability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional 3×2 buried type word line structure is used, then the control circuit can access memory cells through word lines and bit lines, but the unit configuration size is larger and integration density is limited
Solution Approach 1:
The patent transitions from a planar 3×2 word line structure to a 2×2 buried type bit line structure by changing the dimensional arrangement of conductive lines. The bit lines are positioned in the substrate below the active regions, while word lines are formed above, creating a three-dimensional intersection that reduces the footprint area while maintaining electrical connectivity to memory cells
Solution Approach 2:
The patent divides the conductor structure into separate functional layers: bit lines embedded in the substrate and word lines formed above the active regions. This segmentation allows independent optimization of each line type and enables the compact 2×2 configuration by separating the routing functions of bit lines and word lines into different spatial planes
2Ease of manufacture
If line contact holes are used to connect bit lines to active regions, then electrical connection can be achieved, but the manufacturing process becomes more complex and unit size increases
Solution Approach 1:
The bit lines are pre-formed and embedded in the substrate before the active regions are created. This preliminary action eliminates the need for subsequent line contact hole formation, as the bit lines are already in position to receive current from the active regions through direct electrical contact, simplifying the manufacturing process and reducing unit size
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.