SOI Embedded Memory Reducing Leakage Current and Parasitic Capacitance
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Solution Overview
Problem
Integrated circuits (ICs) with embedded memory cells face challenges in performance and scaling due to limitations in power consumption and switching speed, as well as integration difficulties with logic devices, particularly when using traditional bulk silicon substrates.
Innovation Solution
The use of a semiconductor-on-insulator (SOI) substrate with high-κ metal gate (HKMG) logic devices and SONOS/MONOS memory cells, which reduces current leakage, power consumption, and parasitic capacitance, and incorporates a high-κ layer to lower leakage current and increase drain current, while maintaining compatibility with logic device manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional bulk silicon substrates are used for embedded memory, then manufacturing compatibility is maintained, but current leakage and power consumption increase
Solution Approach 1:
The patent changes the substrate parameter from bulk silicon to SOI (semiconductor-on-insulator) structure, which fundamentally alters the electrical characteristics by introducing an insulating layer. This parameter change reduces current leakage and power consumption while the patent simultaneously adjusts process parameters (etching depth, implantation energy) to maintain manufacturing compatibility
Solution Approach 2:
The patent employs a composite structure combining silicon semiconductor layer with buried oxide layer (SOI). This composite material approach creates beneficial electrical isolation properties that reduce leakage current while maintaining mechanical integrity and compatibility with existing CMOS fabrication processes
2Loss of energy
If SOI structures are used to reduce current leakage, then power consumption decreases, but parasitic capacitance and latch-up resistance must be managed
Solution Approach 1:
The patent applies local quality by creating laterally differentiated regions with different doping concentrations and oxide thicknesses. The buried oxide layer thickness varies locally to optimize the balance between reducing parasitic capacitance in active areas and maintaining isolation in non-active areas, thereby managing parasitic effects while minimizing current leakage
3Ease of manufacture
If logic devices and memory cells are integrated on the same substrate, then manufacturing costs are reduced, but performance and scaling are limited
Solution Approach 1:
The patent segments the integrated circuit into distinct logic regions and memory regions on the SOI substrate. Each region can be independently optimized for its specific function while sharing the common SOI infrastructure, enabling simultaneous improvement of logic performance and memory scaling without compromising manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances IC performance, reduces power consumption, and improves scaling by providing better isolation and resistance to latch-up, achieving lower threshold voltage and increased efficiency in memory operations.
Implementation Method 1
incorporates a high-κ layer to lower leakage current and increase drain current
Implementation Method 2
reduces current leakage, power consumption, and parasitic capacitance
Data Source
AI summary
An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.