SOI Epitaxial Layer Covers Isolation Ends to Prevent Contact Misalignment
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Solution Overview
Problem
In semiconductor devices using SOI substrates, misalignment of contact plugs with source/drain regions can lead to malfunction and increased resistance due to conductive paths between MISFETs and the supporting substrate, and lateral siliciding of the SOI layer reduces the SOI layer width, affecting device performance.
Innovation Solution
Forming epitaxial layers on the SOI substrate to cover the ends of isolation regions, thereby preventing contact plug misalignment and reducing lateral siliciding, which maintains the SOI layer width and ensures proper device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to connect to source/drain regions on an SOI substrate, then electrical connection is achieved, but misalignment may occur causing conductive paths to the supporting substrate which increases parasitic resistance and causes malfunction
Solution Approach 1:
An epitaxial layer is formed in advance on the isolation region before contact plug formation. This preliminary action creates a protective structure that prevents misalignment issues during subsequent contact plug formation, ensuring that even if alignment is slightly off, the contact plug remains isolated from the supporting substrate by the epitaxial layer.
Solution Approach 2:
The epitaxial layer acts as an intermediary barrier between the contact plug and the supporting substrate. It mediates the potential harmful interaction by providing an insulating layer that prevents direct electrical connection between the contact plug and the supporting substrate, thereby eliminating parasitic conduction paths.
2Ease of manufacture
If lateral siliciding is performed on the SOI layer, then source/drain regions are formed, but the SOI layer width is reduced which increases resistance and may cause malfunction
Solution Approach 1:
The epitaxial layer is formed preliminarily on the isolation region before siliciding occurs. This pre-formed layer serves as a protective barrier that prevents lateral siliciding from reducing the SOI layer width, thereby maintaining proper resistance characteristics while still allowing source/drain region formation.
Solution Approach 2:
The potential harmful effect of lateral siliciding is converted into a beneficial process by using the epitaxial layer as a sacrificial or protective element. The siliciding reaction is allowed to proceed, but the epitaxial layer prevents it from adversely affecting the SOI layer width, thus converting a potentially harmful process into one that can be controlled and managed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of semiconductor devices by preventing misalignment and reducing parasitic resistance, ensuring normal operation and improved integration density and speed.
Implementation Method 1
ends of an upper surface of an isolation region adjacent to an SOI layer are covered with an epitaxial layer formed on the SOI layer
Data Source
AI summary
A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.