SOI Epitaxial Layer Thickness Control for Plug Penetration Prevention
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Solution Overview
Problem
In semiconductor devices with field effect transistors on SOI substrates, the formation of plugs can lead to electrical conduction between the semiconductor layer and the support substrate due to misalignment, causing operational failures, especially when the epitaxial layer's end portion shape changes from a 'facet structure' to a 'flared structure' as the active region width increases, leading to insufficient etching stoppage and penetration through the buried insulating layer.
Innovation Solution
The epitaxial layer is designed with a 'facet structure' for active regions with widths less than 250 nm and a 'flared structure' for wider regions, with the plug's shortest distance from the element isolation portion increased to prevent penetration, and in wider regions, the epitaxial layer is formed into a comb shape to avoid the 'flared structure', ensuring effective etching stoppage and preventing electrical conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the active region width is increased, then the device performance is improved, but the epitaxial layer forms a 'flared structure' at the end portion which reduces etching stoppage capability and allows plug penetration
Solution Approach 1:
The patent applies local quality by differentiating the epitaxial layer structure based on position: in the central region (first region), the epitaxial layer has a first thickness, while in the end portion region (second region), it has a second thickness greater than the first. This local differentiation ensures that the end portion maintains sufficient etching stoppage capability even when the active region width is increased, preventing plug penetration into the support substrate.
2Device complexity
If photolithography alignment accuracy is reduced, then manufacturing complexity is decreased, but the plug formation position deviates toward the element isolation portion causing electrical conduction between semiconductor layer and support substrate
Solution Approach 1:
The patent implements beforehand cushioning by designing the epitaxial layer with increased thickness at the end portion (second thickness greater than first thickness) before the plug formation process. This pre-established thicker structure acts as a cushion or buffer zone that compensates for potential alignment deviations, ensuring that even if the plug formation position shifts toward the element isolation portion, the etching will still be stopped by the sufficiently thick epitaxial layer, preventing electrical conduction between the semiconductor layer and support substrate.
3Reliability
If the epitaxial layer thickness at the end portion is increased to prevent plug penetration, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the epitaxial layer into two distinct thickness regions: a first region (central area) with a first thickness and a second region (end portion) with a second thickness greater than the first. This segmentation allows the thicker epitaxial layer to be formed only where needed (at the end portion near the element isolation portion) rather than uniformly across the entire active region, thus improving plug penetration prevention while managing manufacturing precision requirements through localized thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents plug penetration into the support substrate, enhancing the reliability of semiconductor devices by ensuring proper etching stoppage and maintaining device operation, even in wider active regions where 'flared structures' might form, thereby reducing defective products and improving manufacturing reliability.
Implementation Method 1
an epitaxial layer formed on a semiconductor layer in an upper part of an SOI substrate
Data Source
AI summary
In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.