SOI ESD Protection Circuit Thermal Durability
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Solution Overview
Problem
Existing ESD protection circuits on SOI substrates are prone to thermal destruction due to high electric consumption, which is not adequately addressed by simply lowering breakdown voltage.
Innovation Solution
A semiconductor integrated circuit with a capacitive transistor and ESD protection circuit, where the capacitive transistor adjusts substrate electric potential and forms a reverse surface channel, enhancing durability against thermal destruction by increasing surge current flow and reducing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the breakdown voltage is lowered to enhance ESD protection, then the ESD protection performance is improved, but the thermal destruction risk increases due to higher electric consumption
Solution Approach 1:
The ESD protection circuit is divided into two separate transistors: a first transistor responsible for ESD protection function and a second transistor dedicated to substrate potential adjustment. This segmentation allows each transistor to be optimized for its specific function, enabling the first transistor to provide ESD protection while the second transistor manages substrate potential to reduce thermal effects, thus resolving the contradiction between ESD protection performance and thermal destruction risk
Solution Approach 2:
The second transistor acts as an intermediary element that adjusts the substrate potential between the first transistor and the ground. By controlling the substrate potential, the second transistor reduces the voltage stress and thermal load on the first transistor, allowing the first transistor to maintain ESD protection performance without suffering from thermal destruction
2Reliability
If the ESD protection circuit is designed with higher surge current capability, then the ESD protection performance is improved, but the thermal destruction risk increases
Solution Approach 1:
The circuit segments the surge current handling function: the first transistor handles the ESD surge current while the second transistor handles the substrate potential adjustment. This segmentation allows the first transistor to be designed for high surge current capability without excessive thermal load, as the second transistor assists in managing the overall circuit conditions
Solution Approach 2:
The second transistor dynamically changes the substrate potential parameter during ESD events. By adjusting the substrate potential, the circuit optimizes the voltage distribution and reduces the thermal load on the first transistor, enabling the first transistor to handle higher surge currents without thermal destruction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances durability against thermal destruction while maintaining necessary ESD protection performance without excessive manufacturing complexity or leakage current issues.
Implementation Method 1
a capacitive transistor and an ESD protection circuit, where the capacitive transistor adjusts substrate electric potential and forms a reverse surface channel
Implementation Method 2
Owing to a substrate bias effect, a threshold voltage of the NMOS is decreased and a trigger voltage having a snapback characteristic is decreased
Implementation Method 3
an ESD (Electro-Static Discharge) protection device
Implementation Method 4
an ESD protection circuit formed on an SOI substrate is thermally damaged by an increased temperature due to a self-heating
Data Source
AI summary
A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.