SOI Wafer Transfer Etch Stop for Boron Diffusion Control

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Solution Overview

Problem

Conventional silicon-on-insulator (SOI) CMOS devices face challenges such as boron diffusion during high temperature processes, which degrades device performance and requires effective methods to control etching processes for precise layer removal.

Innovation Solution

The implementation of a sacrificial substrate with a heavily doped epitaxial layer and an etch stop layer implanted with carbon atoms, followed by a controlled three-step etching process, allows for the precise removal of layers and prevents boron diffusion, thereby ensuring device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional SOI CMOS devices are processed at high temperature, then device fabrication can proceed, but boron diffusion occurs which degrades device performance

Engineering Contradiction:
Improveprocessing temperatureVSAvoiddevice performance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

A silicon-germanium (SiGe) sacrificial layer is introduced as an intermediary between the silicon layer and the substrate. This SiGe layer acts as a diffusion barrier that prevents boron atoms from diffusing into the silicon layer during high temperature processing, thereby protecting device performance while allowing high temperature fabrication procedures to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The SiGe sacrificial layer is designed to be a temporary, disposable structure that serves its protective function during high temperature processing and then is completely removed through selective etching. This disposable layer enables high temperature processing without permanently affecting the final device structure or performance.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If a sacrificial layer is used to prevent boron diffusion, then device performance is maintained, but additional manufacturing steps are required

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The removal of the SiGe sacrificial layer is merged with the existing cavity formation process. The same etching steps used to create cavities in the substrate are also used to remove the SiGe layer, combining two functions into a single process sequence and avoiding additional dedicated removal steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The SiGe layer is engineered with specific compositional parameters (germanium content) that give it distinct etching characteristics compared to silicon. This parameter change allows selective removal of the SiGe layer using etchants that do not attack the silicon layer, enabling clean sacrificial layer removal without affecting the device structure.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If precise layer removal is achieved through controlled etching, then device performance is maintained, but etching process control becomes more difficult

Engineering Contradiction:
Improvelayer thickness uniformityVSAvoidetching process control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Different regions of the structure are given different local qualities through the SiGe layer design. The SiGe layer has localized properties (different composition, thickness, and etching rate) that enable selective removal. This local quality differentiation allows precise control over which layers are removed and which remain, achieving high manufacturing precision through material property variations rather than complex process control.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively eliminates boron diffusion, ensures high uniformity and precision in layer thickness, and maintains device performance by trapping boron atoms within the etch stop layer.

Implementation Method 1

Carbon atoms are implanted into the etch stop layer

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 2

prevents boron diffusion, thereby ensuring device performance

Methodology Applied
Scientific EffectDiffusion Barrier: Diffusion Barrier

Data Source

PatentUS12278139B2Manufacturing method of semiconductor device
Publication Date: 2025.04.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12278139B2 patent drawing
  • US12278139B2 patent drawing
  • US12278139B2 patent drawing

AI summary

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.