SOI Front-End IC Layout With PDSOI PA and FDSOI LNA Integration
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Solution Overview
Problem
Existing CMOS technologies face challenges in integrating high-power PAs, switches, and LNAs in fully integrated FEICs, particularly at small sizes, due to difficulties in manufacturing and higher costs, especially when using bulk or thick film SOI technologies.
Innovation Solution
The integration of PDSOI PAs in a thick film region and FDSOI switches and LNAs in a thin film region within a single semiconductor die, utilizing selective epitaxial growth or local thinning to create the necessary thickness variations, without removing the buried oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk or thick film SOI technologies are used to integrate high-power PAs, switches, and LNAs in fully integrated FEICs, then device performance can be maintained, but manufacturing difficulty increases and costs rise especially at small sizes
Solution Approach 1:
The patent applies local quality by creating distinct thick film and thin film regions within the same semiconductor die. The thick film region (50-200 nm) is specifically engineered for high-power PA devices requiring higher breakdown voltages, while the thin film region (5-50 nm) is optimized for low-noise LNA devices and switches. This spatial differentiation of film thicknesses allows each device type to operate in its optimal electrical environment, maintaining high device performance while enabling standard CMOS manufacturing processes that reduce complexity and cost.
2Ease of manufacture
If thin film SOI technology is used for FDSOI devices, then manufacturing ease and cost are improved, but device performance for high-power applications deteriorates
Solution Approach 1:
The patent segments the semiconductor die into functionally distinct regions with different SOI film thicknesses. By dividing the die into thick film regions for high-power PAs and thin film regions for low-power LNAs and switches, the invention enables each segment to be optimized for its specific performance requirements. This segmentation resolves the contradiction by allowing thin film manufacturing processes to be used overall while providing localized thick film regions where high-power performance is critical.
3Reliability
If varying thickness semiconductor layers are created using selective epitaxial growth or local thinning, then device performance is improved and parasitics are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements parameter changes by varying the SOI semiconductor layer thickness as a key structural parameter across different regions of the die. Using selective epitaxial growth to increase thickness in PA regions or local thinning to reduce thickness in LNA regions, the invention optimizes electrical performance and reduces parasitic effects for each device type. Although these processes add some manufacturing steps, they leverage existing CMOS-compatible techniques, making the increased complexity manageable while delivering significant performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance and reduced parasitics, enabling higher active device performance and lower costs for fully integrated FEICs, with robust passive device performance and reduced need for costly manufacturing adjustments.
Implementation Method 1
The thick film region of the semiconductor layer is formed using selective epitaxial growth
Implementation Method 2
The thin film region of the semiconductor layer is formed using local thinning
Data Source
AI summary
SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions.