SOI Transistor with Ferroelectric Gate for High Density Storage
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Solution Overview
Problem
Current non-volatile storage mechanisms, such as flash memories, face challenges in scaling and bit density due to complex manufacturing processes and compatibility with advanced semiconductor devices, while ferroelectric transistors offer promise but require sophisticated techniques for gate electrode formation and charge carrier manipulation.
Innovation Solution
Implementing a non-volatile storage element with a ferroelectric material in the buried insulating layer of an SOI architecture, combined with a storage mechanism in the gate electrode structure, to achieve increased bit density and flexibility by using ferroelectric materials to control threshold voltage and current flow, allowing for multiple logic states without significant modifications to transistor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory structures are used for non-volatile storage, then data storage capability is achieved, but manufacturing complexity increases and scaling becomes difficult
Solution Approach 1:
The patent merges the storage function directly into the transistor structure by integrating a ferroelectric layer within the gate electrode, combining the transistor and storage capacitor into a single unified structure. This eliminates the need for separate flash memory components while maintaining non-volatile storage capability, thereby reducing manufacturing complexity.
Solution Approach 2:
The gate electrode structure serves dual functions: controlling the channel current (transistor function) and storing data non-volatily through the ferroelectric layer. This multi-functionality eliminates the need for separate storage structures, simplifying the overall device architecture and manufacturing process.
2Reliability
If ferroelectric material is used in gate electrode structure, then non-volatile storage is achieved, but gate electrode formation becomes more complex
Solution Approach 1:
The ferroelectric layer is formed as part of the gate electrode structure during the standard CMOS fabrication process, before final transistor operation. This preliminary integration ensures that the ferroelectric material is properly positioned and prepared, simplifying subsequent manufacturing steps while enabling non-volatile storage functionality.
3Quantity of substance
If transistor dimensions are increased to improve storage density, then bit density increases, but device area and manufacturing complexity increase
Solution Approach 1:
The patent increases storage density by utilizing the vertical dimension through the ferroelectric layer within the gate electrode, rather than increasing horizontal transistor dimensions. This allows multiple logic states to be stored within the same footprint area, increasing bit density without proportionally increasing device area or manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bit density and operational flexibility by providing multiple distinct logic states, doubling the information density without complex modifications to the transistor configuration, and maintains compatibility with advanced manufacturing techniques.
Implementation Method 1
a buried insulating layer formed below the channel region, wherein the buried insulating layer comprises a ferroelectric material so as to provide a storage mechanism for storing information in a non-volatile manner
Implementation Method 2
using ferroelectric materials to control threshold voltage and current flow, allowing for multiple logic states
Data Source
AI summary
The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.