SOI FET Back-Biasing via Vertical Substrate Contacts
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Solution Overview
Problem
The continuous scaling of semiconductor devices leads to increased leakage power due to the scaling of transistors, which affects the performance and power consumption of integrated circuits, particularly in advanced technology nodes, and current back-biasing methods impose area penalties in IC design.
Innovation Solution
A semiconductor device structure with a semiconductor-on-insulator (SOI) substrate and vertical connection elements that allow for back-biasing without consuming active layer area, using a grid of metal grid lines in mechanical contact with the buried insulating layer to apply biasing voltage, thereby eliminating the need for front-side contacts and reducing area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional back-biasing methods are used to reduce leakage power, then leakage current is reduced, but area penalties are imposed in IC design
Solution Approach 1:
The patent moves the back-biasing contact from the front side to the back side of the substrate, utilizing the third dimension (vertical depth) to resolve the area conflict. By forming contact openings through the substrate thickness to reach the buried insulating layer, the solution eliminates the need for front-side area while maintaining back-biasing functionality for leakage reduction
2Productivity
If transistor scaling is continued to increase device density, then packing density is improved, but leakage power increases exponentially
Solution Approach 1:
The patent changes the electrical parameters of the substrate by applying back-biasing voltage through the buried insulating layer. This modifies the threshold voltage and electrical characteristics of transistors, enabling dynamic control of leakage current while maintaining high device density achieved through scaling
3Reliability
If front-side contacts are used for back-biasing, then biasing voltage can be applied to control transistor leakage, but active layer area is consumed
Solution Approach 1:
The patent extracts the back-biasing contact function from the front side and relocates it to the back side of the substrate. By taking out the contact requirement from the active layer area and placing it on the opposite side, the solution maintains transistor leakage control capability while preserving front-side area for transistor fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient back-biasing without area penalties, allowing for dynamic control of transistor performance and reduced leakage current, thereby improving the power efficiency and packing density of integrated circuits.
Implementation Method 1
back-biasing (also referred to as body biasing) is considered as improving the performance of semiconductor devices for very low voltages with extremely low leakage. Herein, a biasing voltage is applied under the buried oxide of SOI substrates having target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VTH
Data Source
AI summary
In one aspect, the present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) substrate composed of an active layer, a substrate and a buried insulating layer which is positioned on an upper surface of the substrate and below a lower surface of the active layer. At least one gate electrode having a channel region below is positioned above an upper surface of the active layer and at least one vertical connection element extends between the upper surface of the substrate and an opposite lower surface of the substrate below the at least one gate electrode. The at least one vertical connection element serves for back-biasing FETs with back-bias contacts at the rear side of the wafer.