SOI FET Dielectric Segmentation for History Effect Control
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Solution Overview
Problem
Partially-Depleted Silicon On Insulator (PDSOI) circuits experience variability in performance due to 'history effects' caused by elevated stimulated leakage and transient capacitive coupling, leading to suboptimal delay-vs.-power characteristics, as the body voltage varies with usage history, making it challenging to minimize variability and maximize switching speed per unit power.
Innovation Solution
A structure is implemented with a high-leakage dielectric over an active region of a FET and a low-leakage dielectric adjacent to it, allowing for customized gate-to-body leakage, which adjusts the history effect by varying the ratio of high-leakage and low-leakage dielectrics to optimize circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform low-leakage dielectric is used throughout the FET structure, then leakage is minimized, but history effects cannot be customized and performance variability remains high
Solution Approach 1:
The patent applies local quality by using different dielectric materials in different regions of the FET structure. Specifically, a first dielectric material is used in the channel region while a second dielectric material with different leakage characteristics is used in the body region. This allows the body region to have customized leakage properties that can be tuned to reduce history effects and performance variability, while the channel region maintains its standard low-leakage characteristics.
2Adaptability or versatility
If gate-to-body leakage is increased to adjust history effects, then history customization is improved, but leakage increases reducing switching speed per unit power
Solution Approach 1:
The patent implements local quality by spatially separating the leakage function from the channel function. The second dielectric material in the body region provides controlled gate-to-body leakage for history effect adjustment, while the first dielectric material in the channel region maintains low leakage for efficient switching. This allows independent optimization of both leakage characteristics in their respective regions.
Solution Approach 2:
The gate dielectric structure is segmented into two distinct regions: a channel region with a first dielectric material and a body region with a second dielectric material. This segmentation allows the body region to have higher controlled leakage for history effect customization without compromising the low leakage performance of the channel region, thus enabling history adjustment with minimal energy loss.
3Loss of energy
If the FET body is fully depleted to reduce leakage, then leakage is minimized, but the floating body effect is lost reducing adaptability for history effect management
Solution Approach 1:
The patent applies local quality by using a second dielectric material in the body region that has different electrical properties from the first dielectric material in the channel region. This second dielectric material allows the body to remain partially depleted, maintaining the floating body effect and enabling body voltage control for history effect management, while still providing sufficient leakage reduction through the dielectric structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tailored history effects, reducing variability and delay in CMOS circuits, achieving the best performance with minimal delay and variability by modifying the gate-to-body leakage, thereby optimizing circuit performance.
Implementation Method 1
a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric.
Data Source
AI summary
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.