SOI FET Gate Junction Layout for Threshold Voltage Stability
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Solution Overview
Problem
Conventional semiconductor fabrication using silicon-on-insulator (SOI) substrates for field-effect transistors often results in unstable threshold voltage due to floating body effects, which can be mitigated by forming conductive-type junctions like NP or PN junctions at the gate structure, but these typically consume significant device area.
Innovation Solution
A field-effect transistor structure is developed with a gate structure layer comprising a first and second region, where the second region includes a conductive-type junction portion, such as an NP or PN junction, formed using trench isolation structures and dopant implantation processes to create a resistor effect without increasing device area, utilizing a polysilicon gate layer and trench isolation structures to maintain the same line width and reduce area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive-type junction portion (NP or PN junction) is formed at the end part of the gate layer to stabilize threshold voltage, then transistor performance and operational stability are improved, but device area consumption increases significantly
Solution Approach 1:
The patent extends the gate structure layer in the vertical direction (Z-axis) to overlap with trench isolation structures, rather than expanding horizontally. This dimensional transition allows the conductive-type junction portion to be formed within the vertical stack, maintaining the same footprint area while achieving threshold voltage stabilization through the junction effect at the gate end region.
Solution Approach 2:
The conductive-type junction portion is nested within the gate structure layer, which itself is stacked over the trench isolation structures. This nested configuration integrates the junction formation within the existing vertical stack, eliminating the need for additional horizontal space while maintaining the electrical functionality for threshold voltage control.
2Reliability
If the gate structure layer is extended to form a conductive-type junction portion, then threshold voltage control is achieved, but the line width and device footprint increase
Solution Approach 1:
Instead of increasing the gate structure line width in the horizontal plane, the patent extends the gate structure layer vertically to overlap with trench isolation structures. This vertical extension achieves the same electrical functionality (conductive-type junction formation) without increasing the horizontal footprint or line width, thus resolving the contradiction between threshold voltage control and device compactness.
3Area of stationary object
If trench isolation structures are used to form the conductive-type junction portion, then area consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The trench isolation structures serve dual functions: (1) providing electrical isolation between adjacent devices, and (2) serving as the substrate for forming the conductive-type junction portion when overlapped by the extended gate structure layer. This multi-functionality eliminates the need for separate structures for isolation and junction formation, reducing overall device complexity while maintaining area efficiency.
Solution Approach 2:
The patent merges the isolation function and junction formation function into a single integrated structure. The gate structure layer extending over the trench isolation structures combines what would traditionally be separate elements (isolation regions and junction regions) into one unified configuration, simplifying the overall device architecture despite the extended gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively stabilizes the threshold voltage and improves transistor performance by forming conductive-type junctions at the gate structure, reducing area consumption and enhancing operational stability, particularly suitable for memory devices with numerous logic circuits.
Implementation Method 1
dopant implantation processes to create a resistor effect
Data Source
AI summary
A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.