SOI Field-Effect Transistor Spacer Structure Without STI Hump Effect
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Solution Overview
Problem
Field-effect transistors fabricated using silicon-on-insulator substrates experience performance issues due to the hump effect and parasitic devices caused by shallow trench isolation regions, particularly at higher gate voltages and scaled channel widths.
Innovation Solution
A structure for a field-effect transistor is designed with a silicon-on-insulator substrate, featuring a gate electrode and a spacer structure that overlaps with the dielectric layer and semiconductor substrate, eliminating the need for shallow trench isolation regions to define the channel width, and incorporating a well and silicide layer for improved electrical isolation and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If shallow trench isolation regions are used to delimit the channel region, then the channel width can be defined, but the hump effect occurs in drain current with increasing gate voltage
Solution Approach 1:
The invention removes the shallow trench isolation regions from the device structure, extracting the problematic element that causes the hump effect. The channel width is instead defined by the spacer structures formed on the sides of the gate electrode, eliminating the source of drain current instability while maintaining precise channel width control.
Solution Approach 2:
The invention introduces spacer structures as intermediary elements that define the channel width. These spacers are formed by depositing material on the sides of the gate electrode and selectively removing excess material, providing a precise and stable channel width definition without the harmful effects of shallow trench isolation regions.
2Manufacturing precision
If shallow trench isolation regions are used to delimit the channel region, then the channel width can be defined, but parasitic devices cause roll-off in drain current at higher gate voltages
Solution Approach 1:
The invention extracts and removes the shallow trench isolation regions that generate parasitic devices. By eliminating these isolation structures, the parasitic effects and associated drain current roll-off at higher gate voltages are removed, while channel width definition is achieved through the spacer-based approach.
3Temperature
If thick dielectric layer is deposited and patterned to form gate dielectric, then high voltage operation is achieved, but device complexity increases
Solution Approach 1:
The invention removes the thick gate dielectric layer and its associated deposition and patterning steps from the device structure. High voltage operation is achieved instead through the spacer structures that extend the effective gate control region, simplifying the manufacturing process while maintaining the desired electrical characteristics.
Solution Approach 2:
Instead of using a thick gate dielectric to achieve high voltage operation, the invention inverts the approach by using spacer structures that extend laterally from the gate electrode. This alternative configuration achieves the same high voltage capability without requiring a thick vertically-oriented dielectric layer.
Data Source
Figure 1
Figure 1A~1B
Figure 2
AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.