SOI FinFET Co-Integration of SiGe and Silicon via Epitaxial Growth
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Solution Overview
Problem
In semiconductor devices, particularly FinFETs, there is a challenge in simultaneously optimizing the performance of pFinFETs and nFinFETs due to material choices that improve one type's performance at the expense of the other, and high-temperature processing can degrade non-silicon based materials like III-V compounds.
Innovation Solution
A method involving a Semiconductor-on-Insulator (SOI) substrate with different semiconductor materials for each region, where epitaxial growth and high-temperature annealing are used to form gate structures, allowing for the creation of FinFET devices with improved performance while preserving temperature-sensitive materials by isolating them from high-temperature processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different materials are used for pFinFET fins and nFinFET fins to improve individual device performance, then device performance is improved, but material compatibility and processing uniformity deteriorate
Solution Approach 1:
The substrate is divided into multiple regions with different semiconductor materials (first region with first material, second region with second material) to allow independent optimization of pFinFET and nFinFET performance while maintaining a unified processing platform
Solution Approach 2:
Different semiconductor materials are selectively placed in different regions of the substrate - silicon-germanium in the first region for pFinFETs and undoped or carbon-doped silicon in the second region for nFinFETs - enabling each device type to have locally optimized material properties
2Ease of manufacture
If high-temperature processing is used to form gate structures, then gate structure formation is achieved, but temperature-sensitive materials are degraded
Solution Approach 1:
Temperature-sensitive semiconductor materials are formed on the substrate before the high-temperature gate structure processing, allowing these materials to be pre-positioned and protected from subsequent high-temperature steps that would otherwise degrade them
Solution Approach 2:
The substrate structure serves as an intermediary platform that allows temperature-sensitive materials to be isolated from high-temperature processing zones, enabling gate formation in regions requiring high temperature while preserving materials in temperature-sensitive regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance FinFET devices with improved material qualities for both pFinFETs and nFinFETs, while protecting temperature-sensitive materials from detrimental high-temperature processing, thus enhancing overall device performance and integration capabilities.
Implementation Method 1
forming a second semiconductor-on-insulator layer through the gate void. The second semiconductor-on-insulator layer is epitaxially grown from the first growth portion of the base semiconductor layer in the second region
Implementation Method 2
epitaxial growth and high-temperature annealing are used to form gate structures, allowing for the creation of FinFET devices with improved performance while preserving temperature-sensitive materials by isolating them from high-temperature processing steps
Data Source
AI summary
A method, and the resulting structure, of a semiconductor device where a first and second gate structure is formed above a Semiconductor-on-Insulator (SOI) material. Following any detrimental processes used to form the first gate structure, the base semiconductor material is exposed and the semiconductor material beneath the second gate structure is removed. A new semiconductor material is grown from the exposed base semiconductor material, and through the second gate structure, creating a device having FET and FinFET devices containing 2 different semiconductor materials.