SOI FinFET With Back Gate Trench For Adjustable Channel Width
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Solution Overview
Problem
Semiconductor devices face challenges in adjusting individual device performance due to uniform fin heights in FinFETs and high costs and limited performance of SOI devices, particularly in addressing short channel effects and optimizing current drive capability per unit footprint.
Innovation Solution
A semiconductor device with a SOI substrate and active areas featuring fin portions and laterally extending portions, allowing for adjustable channel width through the laterally extending portion, combined with a back gate and gate stack configuration, mimicking FinFET advantages while enabling easy adjustment of device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET structure is used to increase current drive capability per unit footprint, then device gain per unit footprint is improved, but individual device performance adjustment becomes difficult due to uniform fin heights
Solution Approach 1:
The active area is divided into first and second sub-areas with fin portions on opposite sides, separated by a back gate trench. This segmentation allows independent control of each fin portion through respective back gate dielectric layers, enabling individual device performance adjustment while maintaining the high current drive capability of FinFET structure
Solution Approach 2:
The back gate trench with conductive material enables dynamic adjustment of device characteristics by applying different voltages to the back gate, allowing flexible control of individual device performance while preserving the uniform fin height advantage for high current drive
2Reliability
If SOI device structure is used to suppress short channel effects, then short channel effects are suppressed, but device performance is limited and manufacturing cost increases
Solution Approach 1:
The device combines SOI substrate structure (with buried dielectric layer for short channel effect suppression) with FinFET active area configuration (providing high current drive capability). This merging allows simultaneous achievement of short channel effect suppression and enhanced device performance with adjustment flexibility
Solution Approach 2:
The back gate trench and dielectric layers are selectively formed in specific regions to provide localized control over channel characteristics, enabling performance optimization in critical areas while maintaining the overall SOI structure benefits
3Adaptability or versatility
If back gate trench is formed to divide active area into sub-areas, then individual device adjustment capability is improved, but device structure complexity increases
Solution Approach 1:
The active area is segmented into sub-areas by the back gate trench, which divides the device into independently controllable sections. This segmentation provides individual device adjustment capability while using a relatively simple trench structure that can be integrated into existing manufacturing processes
Data Source
AI summary
Semiconductor devices and methods for manufacturing the same are provided. An example semiconductor device may include: a Semiconductor on Insulator (SOI) substrate, including a base substrate, a buried dielectric layer and an SOI layer, an active area disposed on the SOI substrate and including a first sub-area and a second sub-area, wherein the first sub-area includes a first fin portion, the second sub-area includes a second fin portion opposite to the first fin portion, and at least one of the first sub-area and the second sub-area includes a laterally extending portion; a back gate arranged between the first fin portion and the second fin portion; back gate dielectric layers sandwiched between the back gate and the respective fin portions; and a gate stack formed on the active area.