Floating Body Capacitor in SOI Memory Cells
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining or increasing capacitance while reducing the size of memory cells, as methods like increasing the lower electrode area or thinning the dielectric layer lead to complex manufacturing processes or reliability issues such as leakage current.
Innovation Solution
A semiconductor memory device utilizing a Silicon-On-Insulator (SOI) substrate with a buried insulating layer and a floating body capacitor formed by accumulated holes, where the buried insulating layer acts as a conducting surface to control the holes, eliminating the need for a physical capacitor and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the lower electrode is increased to maintain or increase capacitance, then the capacitance is improved, but the device complexity and manufacturing difficulty increase due to the need for 3-dimensional structures
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to 3D vertical structures by forming trenches in the substrate and stacking electrodes and dielectric layers vertically. This allows increased capacitance within a smaller footprint area by utilizing the vertical dimension, resolving the contradiction between maintaining capacitance and reducing device area/complexity.
Solution Approach 2:
The patent implements a stacked capacitor structure where multiple electrode-dielectric layers are nested vertically within trenches. The lower electrode, dielectric layer, and upper electrode are arranged in a nested configuration, allowing multiple capacitive elements to occupy the same horizontal footprint, thereby increasing total capacitance without proportionally increasing device area.
2Quantity of substance
If the dielectric layer is made thin to increase capacitance, then the capacitance is improved, but the reliability deteriorates and leakage current increases
Solution Approach 1:
The patent employs composite dielectric structures including ONO (oxide-nitride-oxide) layers and combinations of different dielectric materials with varying thicknesses. By stacking multiple dielectric layers with different properties, the system achieves high capacitance while maintaining reliability, as each layer can be optimized for specific functions (e.g., barrier properties, capacitance, stress control) without requiring any single layer to be excessively thin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved integration and reliable memory operations by using the floating body effect to create a virtual capacitor, enhancing capacitance without the complexity and reliability issues of traditional methods.
Implementation Method 1
a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes is generated in the device-forming layer when the transistor is driven
Data Source
AI summary
A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.