Floating Gate Memory Cell on SOI Substrate
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Solution Overview
Problem
The integration of non-volatile memory, such as flash EEPROM, into a standard CMOS process flow requires additional processing steps and costs due to the need for features like floating gates and control gates, which complicates the manufacturing process and increases costs.
Innovation Solution
The method involves forming a floating gate memory cell on a silicon-on-insulator (SOI) substrate with a buried oxide layer, using the semiconductor layer for the control gate and forming an insulating layer for the floating gate, thereby reducing the number of additional processing steps needed to incorporate the memory cell into the CMOS process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory features (floating gate, control gate) are added to CMOS process flow, then memory functionality is achieved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent merges the formation of control gates and floating gates into a unified process sequence. The control gate is formed first using standard CMOS steps, then the floating gate is formed directly on top using the same deposition and etching equipment, combining two memory-specific features into one integrated manufacturing flow.
Solution Approach 2:
The patent makes the manufacturing process universal by using the same deposition chambers, etching tools, and material layers for both control gate and floating gate formation. This multi-functional approach allows standard CMOS fabrication equipment to produce memory structures without requiring dedicated memory manufacturing lines.
2Reliability
If additional processing steps are added to form floating gate and control gate, then memory cell functionality is achieved, but manufacturing costs increase
Solution Approach 1:
The control gate structure serves dual purposes: it functions as both the control electrode for the memory transistor and as the foundation layer for the floating gate. This self-service approach eliminates the need for separate substrate preparation steps specifically for memory formation, as the control gate formation simultaneously prepares the structure for floating gate deposition.
Solution Approach 2:
The control gate is formed in advance with all necessary insulation layers and conductive layers before the floating gate is added. This preliminary action ensures that when memory-specific steps are introduced, the foundation is already prepared, reducing the need for rework or additional preparatory steps during memory fabrication.
3Adaptability or versatility
If standard CMOS process flow is modified to include memory features, then non-volatile memory integration is achieved, but process flow integrity is compromised
Solution Approach 1:
The patent applies memory-specific modifications only in local regions where memory cells are required, while maintaining standard CMOS process flow in other areas. The floating gate and control gate structures are formed only in memory cell regions, allowing standard logic fabrication to proceed unchanged in other parts of the chip.
Solution Approach 2:
The control gate insulation layer acts as an intermediary between the standard CMOS substrate and the memory-specific floating gate structure. This intermediate layer provides a stable interface that maintains process flow integrity while enabling memory functionality, serving as a buffer between conventional and specialized fabrication steps.
Data Source
AI summary
Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.