SOI Transistor Gate Branch Layout for Kink Effect Reduction
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Solution Overview
Problem
Floating body silicon-on-insulator (SOI) transistors are limited by operating voltage and power due to hot carrier accumulation, and body tied SOI transistors face issues of excessive layout area, poor performance, and kink effects such as threshold voltage shift and memory effects.
Innovation Solution
A semiconductor device with a gate structure featuring a main branch and a sub-branch, where doped regions overlap the branches and source/drain regions, altering the layout design to improve kink effects and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If body tied SOI transistor layout is designed with conventional structure, then voltage and power handling capabilities are extended, but layout area becomes excessive and kink effects are induced
Solution Approach 1:
The gate structure is divided into multiple segments including a main gate branch and one or more sub-branch gates. This segmentation allows the body region to be controlled more efficiently, extending voltage and power handling capabilities while reducing the overall layout area by eliminating the need for excessive body region extensions.
Solution Approach 2:
The gate structure transitions from a conventional single-branch configuration to a multi-branch configuration with sub-branches extending in different directions. This dimensional change in the gate layout enables better control of the body region, improving power handling while compacting the device footprint.
2Power
If body tied SOI transistor layout is designed with conventional structure, then voltage and power handling capabilities are extended, but kink effects such as threshold voltage shift and memory effect are induced
Solution Approach 1:
The gate structure is divided into multiple segments including a main gate branch and one or more sub-branch gates. This segmentation allows the body region to be controlled more efficiently, extending voltage and power handling capabilities while reducing the overall layout area by eliminating the need for excessive body region extensions.
Solution Approach 2:
Different regions of the gate structure have different functions: the main gate branch provides primary control while the sub-branch gates provide localized control over specific portions of the body region. This local quality differentiation enables precise control to prevent kink effects while maintaining overall device performance.
3Manufacturing precision
If doped region is aligned with sub-branch gate, then manufacturing precision is improved, but layout flexibility is reduced
Solution Approach 1:
The aligned doped region serves multiple functions: it acts as a source/drain region for the sub-branch gate, provides electrical connection, and defines the active channel region. This multi-functionality enables precise alignment to be maintained while the overall layout can still be adapted for different device configurations and applications.
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region. The invention includes a plurality of contact plugs, the first doped region does not overlap with the contact plugs, and wherein the plurality of contact plugs comprises a first contact plug and a second contact plug disposed at different sides of the main branch.