SOI Gate and Shared Contact Layout for Leakage-Safe Epitaxial Regions
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Solution Overview
Problem
The formation of plugs on the boundary between the semiconductor layer and the element isolation portion in SOI substrates can lead to leakage defects due to the plug penetrating and contacting the semiconductor substrate, which is exacerbated by the non-uniform growth of epitaxial layers, particularly at rounded edges, compromising the reliability of the semiconductor device.
Innovation Solution
The semiconductor device design includes a configuration where the gate electrodes and sidewall spacers are positioned to ensure that the epitaxial layers and semiconductor layer edges are adequately covered, with shared contact plugs connecting across these layers and spacers to prevent contact with the substrate, using a manufacturing process that ensures proper alignment and coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an epitaxial layer is formed to protrude from the semiconductor layer to prevent plug contact with the substrate, then leakage defects are reduced, but the uniformity of the epitaxial layer width becomes poor due to crystal orientation effects
Solution Approach 1:
The patent applies local quality by forming the epitaxial layer selectively at specific locations where plugs may contact the substrate, rather than uniformly across the entire semiconductor layer. The epitaxial layer is formed to have a greater width at critical regions (where plugs are likely to contact) compared to other regions, creating non-uniform local properties that prevent leakage defects while maintaining overall device functionality
Solution Approach 2:
The patent changes the width parameter of the epitaxial layer at different locations to address the contradiction. By controlling the epitaxial growth process to create varying widths across different regions of the semiconductor layer, the patent ensures sufficient coverage at critical plug contact points while accepting non-uniform width as a necessary compromise to achieve reliable leakage prevention
2Reliability
If the gate electrode is extended to cover the rounded edge of the semiconductor layer, then plug contact with the substrate is prevented, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by extending the gate electrode beyond the conventional boundaries to cover the rounded edge of the semiconductor layer before plug formation. This pre-emptive extension ensures that even if plugs deviate during formation, they cannot contact the substrate, as the extended gate electrode and its sidewall spacer already occupy the protective position
Solution Approach 2:
The extended gate electrode serves multiple functions: it acts as the control electrode for the transistor, provides mechanical support, and serves as a protective barrier preventing plug contact with the substrate. The sidewall spacer formed on the extended gate electrode further enhances this protective function while maintaining a relatively simple overall structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents leakage defects by ensuring comprehensive coverage of the semiconductor layer edges and isolation portions, enhancing the reliability and integrity of the semiconductor device.
Implementation Method 1
an epitaxial layer formed on the semiconductor layer located next to the channel region
Data Source
AI summary
A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.