SOI Transistor Gate Extensions for Lower Resistance and Capacitance
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Solution Overview
Problem
Conventional low noise amplifier (LNA) devices have unsatisfactory design parameters such as high gate resistance and gate to body capacitance, which affect their performance.
Innovation Solution
The semiconductor device design includes gate line extensions protruding outward from the active region and overlapping adjacent indentations, improving transistor performance by optimizing these parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structure is used in LNA devices, then manufacturing is simple, but gate resistance is high and gate to body capacitance is high
Solution Approach 1:
The gate structure is segmented into a gate line within the active area and a gate line extension outside the active area. This segmentation allows the gate to be divided into functional portions: the gate line for primary transistor control and the gate line extension for reducing gate resistance and optimizing capacitance characteristics, thereby resolving the contradiction between performance improvement and structural simplicity.
Solution Approach 2:
The gate structure is extended from a two-dimensional planar configuration into a three-dimensional structure by adding the gate line extension that protrudes from the active area. This dimensional extension provides additional spatial freedom to optimize electrical characteristics (reduce gate resistance and gate-to-body capacitance) without increasing the footprint within the active area, thus improving transistor performance while maintaining manufacturing feasibility.
2Reliability
If gate line extensions are added outside the active area, then gate resistance and gate to body capacitance are reduced, but device structure becomes more complex
Solution Approach 1:
The gate line extension serves multiple functions simultaneously: it extends the gate control region to reduce gate resistance, optimizes the gate-to-body capacitance by positioning the extension outside the active area, and maintains compatibility with conventional fabrication processes. This multi-functionality allows the structure to improve minimum noise figure and other performance parameters without requiring fundamentally new manufacturing techniques.
3Productivity
If gate line extensions overlap with indentations in the active area, then current gain and maximum oscillation frequency are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The indentation structures are formed in the active area before the gate line extensions are deposited. This preliminary formation of indentations creates predetermined alignment references that guide the subsequent gate line extension fabrication. By preparing the substrate structure in advance with these geometric features, the alignment precision requirement is managed through process sequencing rather than requiring ultra-precise single-step alignment.
Data Source
AI summary
A semiconductor device includes a substrate having an active area, a first gate line extending along a first direction on the active area, a first gate line extension adjacent to the first gate line and outside the active area, a second gate line extending along the first direction on the active area and adjacent to the first gate line, and a second gate line extension adjacent to the second gate line and outside the active area. Preferably, the active area includes a first indentation and a second indentation, in which the first gate line extension overlaps the first indentation and the second gate line extension overlaps the first indentation.