SOI Transistor Gate Layout for Kink Effect Suppression
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Solution Overview
Problem
Current body tied SOI transistors face issues with excessive layout area, poor performance, threshold voltage shift, memory effect, and delay due to the kink effect, which limits their voltage and power handling capabilities.
Innovation Solution
A semiconductor device with a gate structure featuring a main branch and a sub-branch, where a doped region overlaps both the main and sub-branches, optimizing the layout design to improve performance and reduce kink effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If body tied SOI transistor layout is designed with conventional structure, then voltage and power handling capabilities can be extended, but excessive area occupation and kink effect occur causing threshold voltage shift and performance degradation
Solution Approach 1:
The gate structure is segmented into a main branch and a sub-branch extending in different directions. This segmentation allows the doped region to overlap with both branches, achieving effective body tying and kink effect suppression while reducing the overall layout area occupation compared to conventional structures.
2Power
If body tied SOI transistor layout is designed with conventional structure, then voltage handling capability is improved, but kink effect induces threshold voltage shift and memory effect
Solution Approach 1:
The gate structure extends in multiple directions (main branch along first direction, sub-branch along second direction), utilizing dimensional expansion to achieve better overlap with the doped region. This multi-directional arrangement suppresses the kink effect more effectively than conventional single-direction layouts, improving threshold voltage stability while maintaining voltage handling capability.
3Ease of manufacture
If doped region overlaps only main branch of gate structure, then manufacturing is simpler, but performance optimization and kink effect reduction are insufficient
Solution Approach 1:
The gate structure is divided into main branch and sub-branch segments that extend in different directions. The doped region is designed to overlap with both segments, achieving superior kink effect suppression and performance optimization. While slightly more complex than single-branch designs, the segmented structure remains manufacturable using standard semiconductor fabrication processes.
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.