SOI Device Conducting Member for Gate-Substrate Coupling
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Solution Overview
Problem
Semiconductor switch devices with silicon-on-insulator (SOI) structures face challenges such as current leakage during fabrication, leading to non-linearity and reduced power handling capabilities due to plasma charging, which affects their performance and efficiency in communication systems.
Innovation Solution
A semiconductor-on-insulator (SOI) structure with a substrate, insulator layer, and semiconductor layer, including conductivity regions, a gate structure, and conductor elements that electrically contact the substrate and gate, with conducting members to couple these elements, enhancing the device's electrical connectivity and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI structure is used to reduce parasitic capacitance and substrate loss, then switch device performance is improved, but current leakage occurs due to plasma charging during fabrication
Solution Approach 1:
The patent extracts the problematic plasma charging effect from the fabrication process by implementing a specific sequence of steps: forming the SOI structure first, then subsequently forming conductor elements that contact the substrate, and finally forming conducting members that electrically couple these conductor elements to the gate structure. This extraction approach removes the harmful plasma charging effects that occur during standard fabrication while preserving the beneficial SOI structure properties.
Solution Approach 2:
The patent applies preliminary action by pre-forming the conductor elements that contact the substrate before forming the conducting members that provide electrical coupling. This preliminary configuration of conductor elements positions them to receive and dissipate plasma charges before they can cause harmful effects during subsequent fabrication steps, thereby preventing current leakage while maintaining device performance.
2Ease of manufacture
If conventional fabrication process is used, then manufacturing is straightforward, but plasma charging causes non-linearity and reduced power handling capability
Solution Approach 1:
The patent segments the fabrication process into distinct sequential steps: (1) forming the SOI structure, (2) forming conductor elements contacting the substrate, (3) forming conducting members providing electrical coupling, and (4) completing device fabrication. This segmentation allows each step to be optimized independently, maintaining ease of manufacture while systematically addressing plasma charging issues to improve linearity and power handling capability.
Data Source
AI summary
A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.