SOI Heat Sink Array for Uniform Thermal Distribution
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Solution Overview
Problem
High power silicon-on-insulator (SOI) devices face significant heat dissipation issues due to the low thermal conductance of the buried oxide layer, leading to non-uniform temperature distribution and potential device breakdown, with existing heat sink arrangements either ineffective or area-consuming.
Innovation Solution
A heat sink array with varying width and depth is integrated into the SOI device, where the heat sink width and volume incrementally decrease from the center to the edge, ensuring even thermal conductance and reduced area consumption, allowing for efficient heat dissipation and uniform temperature distribution across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If heat sinks are integrated into each individual SOI device in a high power device array, then heat dissipation capability is improved, but device area is consumed and on-state resistance increases
Solution Approach 1:
Multiple individual heat sinks are merged into a single shared heat sink structure that serves multiple SOI devices. The heat sink is formed as a continuous region extending beneath multiple device pairs, allowing heat from different devices to be dissipated through a common thermal pathway, thereby reducing total area consumption while maintaining heat dissipation capability.
Solution Approach 2:
The shared heat sink structure performs multiple functions: it dissipates heat from multiple different SOI devices simultaneously, serves as a common thermal management solution for the entire device array, and reduces the overall footprint compared to individual heat sinks for each device.
2Loss of energy
If heat sinks are integrated into each individual SOI device in a high power device array, then heat dissipation capability is improved, but on-state resistance increases
Solution Approach 1:
The shared heat sink configuration reduces the number of discrete heat sink structures, thereby reducing the total parasitic resistance introduced by multiple heat sink interfaces and contacts. This lowering of parasitic resistance directly improves the on-state resistance of the high power device.
3Ease of manufacture
If uniform heat sink arrangements are used across the device array, then manufacturing is simplified, but non-uniform temperature distribution occurs with hot spots at the center
Solution Approach 1:
The heat sink structure is designed with spatially varying properties: the width of the heat sink region decreases from the center toward the edges of the device array. This non-uniform geometry creates different thermal conductances in different regions, with higher thermal conductance at the center to handle the higher heat generation density, thereby achieving uniform temperature distribution across the device.
Solution Approach 2:
The thermal conductance parameter of the heat sink is varied spatially by changing the width dimension of the heat sink region. This parameter change allows the heat sink to adapt to the non-uniform heat generation profile of the device array, with higher thermal conductance where heat generation is higher (center) and lower thermal conductance at the edges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a substantially even temperature distribution across the semiconductor device, preventing hot spots and improving device reliability, while reducing on-state resistance and area usage.
Implementation Method 1
The heat sink 16 is typically arranged to transfer heat from the active area of the device 1 to the substrate 10
Data Source
AI summary
An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.