SOI High Voltage Isolation Trenches for Mixed-Signal ICs

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Solution Overview

Problem

Conventional integrated circuit technologies fail to effectively isolate very high voltage circuitry from low voltage circuitry on a single semiconductor die, as existing isolation methods are insufficient to handle voltages exceeding 1000V, necessitating separate dies and inadequate insulator thickness in silicon-on-insulator (SOI) technology.

Innovation Solution

Combining silicon-on-insulator (SOI) technology with high voltage lateral isolation trenches at two levels, including wide trenches at the active silicon and wafer backside, and adding thick isolation films, along with an epoxy-based wafer backside film to completely isolate low voltage components from 1000V levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional integrated circuit isolation technology is used, then manufacturing simplicity is maintained, but electrical isolation between high voltage and low voltage circuitry cannot be achieved

Engineering Contradiction:

Improveelectrical isolationVSAvoidisolation structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is segmented into multiple components: shallow trenches filled with dielectric material, deep trenches extending through the substrate, and thick epitaxial layers. Each segment performs a specific isolation function, collectively achieving complete electrical isolation between high voltage and low voltage circuitry while maintaining a systematic fabrication process

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar isolation to three-dimensional multi-level isolation by creating trenches at different depths (shallow and deep levels) and adding vertical epitaxial layers. This dimensional approach enables sufficient isolation distance for high voltage applications without requiring excessive lateral space

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If silicon-on-insulator (SOI) technology is used, then vertical isolation is improved, but insulator thickness is insufficient for voltages exceeding 5000V

Engineering Contradiction:

Improvevertical isolationVSAvoidinsulator thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent merges SOI technology with lateral trench isolation structures. The SOI buried oxide layer provides vertical isolation, while additional lateral trenches and thick epitaxial layers are integrated to extend the isolation path length. This combination achieves both vertical and lateral isolation necessary for high voltage applications

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The isolation structure uses composite materials including silicon dioxide (SOI box), silicon nitride (trench filling), and heavily doped epitaxial silicon layers. Each material contributes specific properties: electrical insulation, mechanical strength, and voltage blocking capability, collectively achieving isolation for voltages exceeding 5000V

Inventive Principle:

Principle #40Composite materials

3Reliability

If high voltage and low voltage circuitry are placed on separate dies, then electrical isolation is achieved, but device complexity and packaging requirements increase

Engineering Contradiction:

Improveelectrical isolationVSAvoidmulti-die packaging

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges high voltage and low voltage circuitry onto a single semiconductor die by implementing comprehensive isolation structures. The multi-level trenches and thick epitaxial layers enable both circuit types to coexist on the same substrate, eliminating the need for separate dies and complex multi-die packaging while maintaining electrical isolation

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If thick isolation films are added to provide overhead isolation, then electrical isolation between voltage levels is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveoverhead isolationVSAvoidfabrication process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The thick epitaxial isolation layers are formed preliminarily during the early stages of device fabrication, before subsequent processing steps. The trenches are etched and filled with dielectric materials in advance, establishing the isolation framework early in the manufacturing process and simplifying later fabrication steps

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7880261B2Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip

Publication Date: 2011.02.01 NAT SEMICON CORP

AI summary

An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.