SOI HKMG Memory Transistor Layout to Prevent CMP Dishing
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Solution Overview
Problem
Existing silicon-on-insulator (SOI)-based High-k Metal Gate (HKMG) transistors face challenges in integrating low-voltage and high-voltage applications on the same substrate due to dishing effects during polishing processes, which are undesirable in CMOS fabrication.
Innovation Solution
The integration of low-voltage and high-voltage transistors on a single SOI substrate, where high-voltage transistors utilize multiple HKMG structures as dummy gate structures to prevent dishing effects during polishing, allowing for the concurrent formation of HKMG structures for both voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polishing processes are used on SOI substrates with HKMG structures, then manufacturing efficiency is maintained, but dishing effects occur that degrade manufacturing precision
Solution Approach 1:
The substrate surface is segmented into different regions: first regions with low-voltage transistors and second regions with high-voltage transistors. This segmentation allows different polishing approaches to be applied to different regions, preventing dishing effects in the high-voltage regions while maintaining manufacturing efficiency across the entire substrate.
Solution Approach 2:
Different structural configurations are applied to different regions of the substrate. The first regions contain conventional low-voltage transistor structures, while the second regions contain high-voltage transistor structures with specific modifications (such as adjusted gate lengths or protective layers) that make them resistant to dishing effects during polishing, thereby achieving local optimization of surface flatness.
2Adaptability or versatility
If low-voltage and high-voltage transistors are integrated on the same substrate, then device versatility is improved, but manufacturing complexity increases due to conflicting process requirements
Solution Approach 1:
The substrate is divided into first regions for low-voltage transistors and second regions for high-voltage transistors. This spatial segmentation allows each region to be optimized for its specific voltage requirement while using a unified manufacturing process flow, thereby integrating multiple voltage levels without proportionally increasing process complexity.
Solution Approach 2:
A single unified manufacturing process is developed that can simultaneously fabricate both low-voltage and high-voltage transistors on the same substrate. The process uses common materials and steps for both transistor types, with only minor regional variations, thereby achieving multi-functionality and reducing overall manufacturing complexity compared to separate process lines.
Data Source
AI summary
A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.