High-Voltage Transistors on SOI Substrates via Bulk Access
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) substrates face difficulties in integrating high-voltage transistors due to complex processing requirements and the inability of conventional techniques to sustain high voltage operations, leading to potential transistor breakdown.
Innovation Solution
A semiconductor device is formed using a SOI substrate with a semiconductor layer, a bulk substrate, and an insulating layer, where an isolation structure extends through the insulating layer and terminates in the bulk substrate, and a gate structure is formed between source and drain regions on the semiconductor layer, allowing for high-voltage operations by reducing electric field stress and preventing transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to integrate HV transistors on SOI substrates, then transistor integration is achieved, but processing complexity increases and manufacturing cost increases
Solution Approach 1:
The device is segmented into distinct functional regions: a first device region containing the HV transistor with source/drain regions extending into the bulk substrate, and a second device region for low-voltage devices. This spatial segmentation allows each region to be optimized independently, enabling reliable HV operation while simplifying the overall integration process on SOI substrates.
Solution Approach 2:
The invention utilizes the vertical dimension by extending source and drain regions from the semiconductor layer down into the bulk substrate. This three-dimensional configuration allows the HV transistor to access the bulk substrate for high-voltage operation while maintaining compatibility with standard SOI processing techniques.
2Reliability
If conventional techniques are used to integrate HV transistors on SOI substrates, then transistor integration is achieved, but manufacturing cost increases
Solution Approach 1:
By segmenting the substrate into first and second device regions with different functionality, the invention enables HV transistor integration using modified standard SOI processes rather than requiring entirely new complex processes, thereby reducing manufacturing cost while maintaining reliability.
Solution Approach 2:
The SOI substrate structure is made multi-functional: it can simultaneously support both high-voltage devices (utilizing bulk substrate access) and low-voltage devices (utilizing the semiconductor layer), as well as serve as a platform for both types of devices in the same integrated circuit, improving ease of manufacture.
3Productivity
If the semiconductor layer structure is used for HV transistors, then integration on SOI substrate is achieved, but the transistor cannot sustain high voltage operations due to breakdown
Solution Approach 1:
The critical innovation is extending the source and drain regions vertically from the semiconductor layer into the bulk substrate. This dimensional change provides a low-resistance path for high-voltage current and distributes the electric field stress, enabling the transistor to sustain high voltage operations without breakdown while maintaining integration on the SOI substrate.
Solution Approach 2:
The bulk substrate acts as an intermediary that mediates between the semiconductor layer and the high-voltage operation requirements. By extending source/drain regions into the bulk substrate, it provides the necessary electrical pathways and field distribution characteristics for high-voltage operation, preventing breakdown while enabling productivity.
Data Source
AI summary
The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.