SOI Structure With III-V Etch Stop for Uniform Silicon Thickness
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Solution Overview
Problem
Conventional silicon-on-insulator (SOI) structures face challenges in producing wafers with low yield and high cost, often resulting in thickness variation and defects due to the use of heavily doped boron etch stops, which cause nonuniform doping and excessive surface roughness.
Innovation Solution
The implementation of an undoped III-V etch stop layer in contact with the silicon film, utilizing high selectivity between silicon and III-V materials to achieve a total thickness variation of less than 1 nm, replacing the conventional heavily doped boron etch stop layer to minimize surface roughness and threading dislocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If heavily doped boron etch stop is used, then etching selectivity is achieved, but surface roughness increases and thickness uniformity deteriorates
Solution Approach 1:
The patent changes the material parameter from boron-based etch stop to silicon nitride etch stop, which fundamentally alters the etching characteristics. Silicon nitride provides high etching selectivity against silicon while maintaining smooth surface finish, thereby resolving the contradiction between etching effectiveness and surface quality.
Solution Approach 2:
The patent employs a sacrificial silicon nitride etch stop layer that is deposited and then completely removed after serving its purpose during the etching process. This disposable layer enables precise thickness control during fabrication and is subsequently eliminated, leaving the desired smooth silicon surface without boron contamination.
2Productivity
If conventional SOI manufacturing methods are used, then production cost is reduced, but yield decreases and defects increase
Solution Approach 1:
The silicon nitride layer serves as an intermediary etch stop that enables precise thickness control during the SOI manufacturing process. This intermediary layer allows for better control of the device layer thickness, reducing defects and improving yield while maintaining cost-effectiveness through a straightforward deposition and etching sequence.
3Manufacturing precision
If boron doping is applied to control etching, then etching selectivity is improved, but doping uniformity deteriorates and defects are introduced
Solution Approach 1:
The patent extracts the doping function from the etch stop layer by using undoped silicon nitride instead of doped boron. The etching selectivity is achieved through the material properties of silicon nitride itself rather than through doping, eliminating the uniformity problems associated with boron diffusion and implantation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of SOI structures with significantly reduced thickness variation and improved surface smoothness, enhancing the performance and uniformity of silicon wafers by using epitaxially grown III-V etch stop layers, such as gallium phosphide, to facilitate precise etching and minimize defects.
Implementation Method 1
The implementation of an undoped III-V etch stop layer, grown using low-temperature techniques, provides a high selectivity between silicon and III-V materials, allowing for precise thickness control and minimizing surface roughness
Implementation Method 2
an undoped III-V etch stop layer, grown using low-temperature techniques
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.