SOI Image Sensor Pixel Layout With Vertical Transfer Gate
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Solution Overview
Problem
Existing image sensors have a large size of unit pixels, which can limit their performance and efficiency in light detection.
Innovation Solution
The image sensor design incorporates a base substrate with a silicon on insulator (SOI) structure, featuring a buried insulation layer and a semiconductor layer, along with a photo sensing device, a buried impurity region, and transfer gates that extend vertically through the substrate, minimizing pixel size while enhancing charge transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the unit pixel size is reduced to improve light detection performance, then the detection efficiency is improved, but the manufacturing precision and device layout become more difficult
Solution Approach 1:
The transfer gate is configured to extend in the vertical direction through the semiconductor layer and buried insulation layer, utilizing the third dimension to reduce the horizontal footprint of the pixel. This vertical extension allows charge transfer functionality to be achieved without increasing the planar pixel area, thereby maintaining high light detection performance while simplifying manufacturing precision requirements.
Solution Approach 2:
The pixel structure is divided into distinct functional regions including the photo sensing device, buried impurity region, transfer gate, and planar gate. This segmentation allows each component to be optimized independently, with the transfer gate specifically designed to extend vertically to minimize its horizontal space requirement, thus reducing overall pixel size while maintaining manufacturing feasibility.
2Productivity
If the transfer gate extends vertically through the substrate to improve charge transfer efficiency, then the charge transfer performance is improved, but the device complexity increases
Solution Approach 1:
The vertically extending transfer gate serves multiple functions: it enables efficient charge transfer from the photo sensing device to the floating diffusion region, acts as a barrier to prevent charge leakage, and defines the pixel boundary. By consolidating these functions into a single vertical structure, the gate complexity is managed while achieving high charge transfer efficiency.
Solution Approach 2:
The transfer gate is nested within the vertical stack of the pixel structure, extending through the semiconductor layer and buried insulation layer. This nested configuration allows the transfer gate to be integrated into the existing pixel architecture without requiring separate lateral space, thereby improving charge transfer efficiency while minimizing additional device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the pixel size, minimizes the short channel effect, and enhances the transconductance of source follower transistors, leading to improved light detection performance and operational characteristics.
Implementation Method 1
a photo sensing device in the substrate layer, the photo sensing device including an impurity region having a second conductive type
Data Source
AI summary
Image sensors may include a base substrate including a substrate layer, a buried insulation layer on the substrate layer, and a semiconductor layer on the buried insulation layer, a photo sensing device in the substrate layer, a buried impurity region spaced apart from the photo sensing device in an upper portion of the substrate layer, a transfer gate including a vertical gate extending through the semiconductor layer and the buried insulation layer and extending into an inner portion of the substrate layer, which is between the photo sensing device and the buried impurity region, a planar gate on the semiconductor layer, and a gate insulation layer between the substrate layer and the planar gate.