SOI Insulation Wells for Thermal Management
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Solution Overview
Problem
The high cost and inefficiency of existing SOI semiconductor wafer manufacturing processes, particularly due to the continuous buried oxide layer which hinders heat dissipation in power devices integrated on the same die, and the complexity of integrating power devices with signal circuits on the same semiconductor die.
Innovation Solution
A process involving trench etching, epitaxial growth, thermal annealing, and chemical-mechanical planarization to create SOI-insulation wells that allow for separate heat dissipation in power components while maintaining SOI insulation for signal circuits, by forming buried channels and converting diaphragms into silicon oxide, enabling effective thermal management and integration of power and signal circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous buried oxide layer is used for SOI insulation, then electrical insulation between substrate and epitaxial layer is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The continuous buried oxide layer is segmented into discrete oxide-filled wells separated by regions where silicon columns remain. This segmentation allows electrical insulation to be provided only where needed (in the oxide-filled wells) while preserving heat dissipation pathways through the continuous silicon regions, thereby resolving the contradiction between insulation effectiveness and thermal management.
Solution Approach 2:
The patent applies oxide insulation locally rather than continuously, creating a patterned structure where oxide-filled wells provide insulation for signal circuits while adjacent silicon-rich regions provide thermal conduction pathways. This local application of insulation quality allows simultaneous achievement of electrical isolation and thermal management.
2Manufacturing precision
If two starting substrates are bonded for SOI wafer manufacturing, then SOI structure quality is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and removes portions of the substrate to create trenches that are subsequently filled with oxide, rather than bonding two complete substrates. This extraction approach creates the necessary SOI structure with embedded oxide regions while using only a single substrate, thereby reducing manufacturing complexity and cost while maintaining structural quality.
Solution Approach 2:
Instead of achieving SOI structure through substrate bonding (a planar operation), the patent introduces a vertical dimension by etching trenches and filling them with oxide material. This dimensional approach allows oxide insulation to be integrated within the substrate thickness, eliminating the need for substrate bonding and simplifying the manufacturing process.
3Adaptability or versatility
If power devices and signal circuits are integrated on the same die, then device functionality is improved, but thermal management difficulty increases
Solution Approach 1:
The die is segmented into distinct functional regions: oxide-filled wells for signal circuits requiring electrical insulation, and continuous silicon regions for power devices requiring thermal conduction. This spatial segmentation allows both signal and power devices to coexist on the same die while each operates in an environment optimized for its thermal requirements.
Solution Approach 2:
Different thermal management qualities are applied locally across the die: oxide-filled regions provide electrical insulation for signal circuits, while silicon-rich regions provide thermal pathways for power devices. This local differentiation of material quality enables integrated functionality with appropriate thermal characteristics for each device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process reduces the 'loading effect' in trench etching, ensures planarity for advanced photolithography, and allows for reliable integration of power and signal components with reduced thermal disturbances, enhancing manufacturing efficiency and device performance.
Implementation Method 1
the trenches are closed by growth of a monocrystalline epitaxial layer
Implementation Method 2
Buried cavities are thus formed, which are remodeled by a thermal 'annealing' process. Annealing exploits the deoxidizing atmosphere rich in hydrogen, which has remained trapped inside the buried cavities during the epitaxial growth
Implementation Method 3
a thermal oxidation step is carried out, in which the walls between adjacent buried channels are completely converted into silicon oxide
Data Source
AI summary
A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.