Integrated Capacitors in SOI ICs for High-Voltage Leakage
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Solution Overview
Problem
Integrated circuits face challenges in incorporating capacitors, particularly in analogue and high-voltage circuits, where larger capacitances and higher operating voltages require thicker or higher-quality dielectrics, leading to increased device size and cost, and existing combinations of integrated capacitances are difficult to achieve effectively.
Innovation Solution
A silicon-on-insulator (SOI) integrated circuit design that incorporates a parallel arrangement of multiple capacitors, including a metal-insulator-metal (MIM) capacitor and three other capacitors using the substrate, n-type semiconductor layers, insulating layers, and polysilicon structures, with buried oxide and trench isolation structures as dielectrics, to increase capacitance per unit area while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker or higher-quality dielectric is used to avoid leakage in high-voltage circuits, then reliability is improved, but device size and cost increase
Solution Approach 1:
The patent combines multiple capacitor types (MIM, MOS, and diffusion capacitors) into a single integrated capacitor structure, merging their functions to achieve high capacitance values suitable for high-voltage circuits while maintaining compact device size. The integrated capacitor integrates the advantages of different capacitor types to provide sufficient capacitance without requiring thicker dielectric layers.
Solution Approach 2:
The patent uses a composite structure combining metal-insulator-metal (MIM) capacitors with metal-oxide-semiconductor (MOS) capacitors and diffusion capacitors. This composite approach allows the integrated capacitor to achieve high capacitance values and maintain reliability in high-voltage applications without increasing device size, as each material contributes its strengths to the overall structure.
2Quantity of substance
If larger capacitances are used in analogue circuits, then circuit performance is improved, but device size increases
Solution Approach 1:
The patent merges MIM capacitors, MOS capacitors, and diffusion capacitors into a single integrated capacitor that provides large total capacitance. By combining the capacitance contributions of multiple capacitor types in parallel, the integrated capacitor achieves high capacitance values needed for analogue circuit performance while occupying minimal device area.
Solution Approach 2:
The patent utilizes vertical stacking of multiple capacitor structures (MIM, MOS, and diffusion capacitors) to increase capacitance in the vertical dimension rather than expanding horizontally. This allows the integrated capacitor to provide large capacitance values while maintaining a compact footprint on the device area.
3Adaptability or versatility
If integrated passive components are added to the IC, then circuit functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for MIM capacitors, MOS capacitors, and diffusion capacitors into a single unified manufacturing process. The integrated capacitor is formed using standard CMOS fabrication steps that can be incorporated into existing production lines, thereby improving circuit functionality without significantly increasing manufacturing complexity.
Solution Approach 2:
The patent designs the integrated capacitor structure to serve multiple functions within the same fabrication process. The same manufacturing steps that create the MIM capacitor also form the MOS and diffusion capacitor components, making the process universal and avoiding the need for separate specialized manufacturing steps for each capacitor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly increases capacitance per unit area with acceptable linearity, allowing for efficient use of volume and maintaining the benefits of integrated passive components without adding complexity to the fabrication process, thus addressing the challenges of integrating capacitors in challenging circuit types.
Implementation Method 1
the second capacitor comprises as plates the substrate and an n-type one of the plurality of semiconductor layers, and comprises the buried oxide layer as dielectric
Implementation Method 2
the third capacitor comprises as plates the polysilicon layer and a further n-type one of the plurality of semiconductor layers and comprises the insulating layer as dielectric
Implementation Method 3
the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric
Data Source
AI summary
There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; andthe fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.