SOI Active Interposer Via Structure for Latch-Up Suppression
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Solution Overview
Problem
Fabricating CMOS devices on silicon-based interposers is prone to short-channel and latch-up effects, which affect device performance in three-dimensional integrated circuits.
Innovation Solution
An SOI active interposer is developed, featuring a CMOS inverter with PMOS and NMOS transistors on an SOI substrate, with via holes and insulating media to suppress these effects, and copper diffusion barrier layers and seed layers for electrical interconnection and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS devices are fabricated on silicon-based interposers to achieve electrical interconnection, then interconnection functionality is achieved, but short-channel effect and latch-up effect occur which degrade device performance
Solution Approach 1:
An SOI interposer is introduced as an intermediary component between chips to enable electrical interconnection while avoiding the harmful effects of traditional silicon-based interposers. The SOI interposer includes an SOI substrate with an SOI via hole formed between the PMOS and NMOS transistors, which penetrates through the top silicon layer and silicon dioxide layer to reach the silicon substrate. This SOI via hole structure acts as an effective isolation mechanism that eliminates latch-up and short-channel effects while maintaining the electrical interconnection function.
2Quantity of substance
If three-dimensional packaging is implemented to achieve high-density packaging, then packaging density is improved, but device performance is degraded due to short-channel and latch-up effects
Solution Approach 1:
The SOI interposer serves as a mediator that enables three-dimensional packaging with high density while maintaining device performance. By using the SOI substrate structure with the SOI via hole, the patent achieves vertical stacking of chips with electrical interconnection through the interposer, attaining high packaging density without suffering from the short-channel and latch-up effects that plague traditional silicon-based approaches.
3Productivity
If TSV interposer technology is used to maximize stacking density and reduce interconnection length, then packaging efficiency is improved, but device performance deteriorates due to CMOS device fabrication issues on silicon substrates
Solution Approach 1:
The patent changes the substrate parameter from traditional silicon-based interposer to SOI (Silicon-On-Insulator) interposer. This parameter change fundamentally alters the electrical characteristics of the interposer, enabling the fabrication of CMOS devices without experiencing short-channel and latch-up effects. The SOI via hole structure further modifies the electrical parameters by providing effective isolation, thereby maintaining high packaging efficiency while improving device performance.
Data Source
AI summary
Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.