SOI Substrate Isolation Region for RF Parasitic Coupling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor-on-insulator (SOI) structures face challenges in reducing parasitic coupling and harmonic distortion in RF devices due to high resistivity substrates, which are not adequately addressed by current methods.

Innovation Solution

A method involving the formation of an isolation region in the handle substrate using arsenic or oxygen ion implantation, thermal oxide deposition, or epitaxial deposition to create a p/n junction, dielectric, or semi-insulating material layer under the dielectric layer, which impedes charge carrier transfer and reduces parasitic coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If high resistivity substrate is used in SOI structures, then parasitic coupling and harmonic distortion are reduced, but charge carrier transfer between devices increases causing cross-talk

Engineering Contradiction:
Improveparasitic couplingVSAvoidcharge carrier transfer
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The substrate is segmented into isolated regions through ion implantation that creates depleted zones beneath each device. These depleted regions act as electrical barriers that segment the continuous substrate into isolated islands, preventing charge carrier transfer between adjacent devices while maintaining high resistivity for reducing parasitic coupling.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The substrate is modified locally beneath each device through selective ion implantation to create depleted regions with different electrical properties. These local modifications create low carrier concentration zones that act as isolation barriers, while the rest of the substrate maintains high resistivity for optimal RF performance.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If ion implantation is used to create isolation regions, then parasitic coupling is suppressed, but manufacturing complexity increases

Engineering Contradiction:
Improveparasitic couplingVSAvoidmanufacturing process
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The isolation regions are created through ion implantation performed early in the fabrication process, before device formation. This preliminary action establishes the electrical isolation framework in advance, simplifying subsequent processing steps and enabling standard RF device fabrication without additional isolation formation steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively suppresses cross-talk and power losses between RF devices by embedding an isolation region in the handle substrate, enhancing signal integrity and reducing harmonic distortions.

Implementation Method 1

implanting As+ ions through a front surface of a single crystal semiconductor handle substrate to thereby form an isolation region comprising arsenic-doped semiconductor

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

thermally oxidizing a front surface of a single crystal semiconductor handle substrate to thereby grow an oxide layer on the front surface

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Implementation Method 3

epitaxially depositing an epitaxial arsenic-doped silicon layer on a front surface of a single crystal semiconductor handle substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 4

which impedes charge carrier transfer and reduces parasitic coupling

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS20250259884A1High resistivity silicon-on-insulator substrate comprising an isolation region
Publication Date: 2025.08.14 GLOBALWAFERS CO LTD
  • US20250259884A1 patent drawing
  • US20250259884A1 patent drawing
  • US20250259884A1 patent drawing

AI summary

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.