SOI Isolation Trench With Underlap Dielectric For Short Circuit Prevention

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Solution Overview

Problem

Current microelectronic device fabrication methods using SOI substrates with STI isolation trenches face issues of material degradation during cleaning and etching steps, leading to potential short circuits due to partial removal of dielectric material, and existing solutions do not completely prevent these issues.

Innovation Solution

A method involving the deposition of a second dielectric layer with thicker portions extending under active regions and filling the trench with multiple dielectric layers to create an isolation trench with enhanced resistance and prevent voids, ensuring electrical insulation even if material is partially withdrawn.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thin liner layer is deposited to protect the isolation trench during cleaning and etching steps, then the resistance of the isolation trench is improved, but the liner layer itself is removed during contact etching, destroying the protection

Engineering Contradiction:
Improveisolation trench protectionVSAvoidliner layer removal causing short circuit
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating a non-uniform dielectric layer with varying thickness: a thin liner layer at the trench walls for protection, and a thicker bulk layer filling the trench center for robust insulation. This local differentiation allows the thin liner to provide protection where needed while the thick bulk ensures insulation even if partially removed during processing.

Inventive Principle:
Principle #3Local quality

2Productivity

If the isolation trench is made narrow to increase device density, then productivity is improved, but the trench becomes more susceptible to material removal and short circuits

Engineering Contradiction:
Improvedevice densityVSAvoidisolation trench integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent uses composite materials by combining a thin protective liner layer (e.g., silicon nitride or oxide) with a bulk dielectric material (e.g., silicon dioxide) to form a composite isolation structure. This composite approach allows the narrow trench to maintain both protection (from the liner) and insulation (from the bulk dielectric), enabling high device density without sacrificing reliability.

Inventive Principle:
Principle #40Composite materials

3Reliability

If multiple dielectric layers are deposited to ensure insulation, then reliability is improved, but the process complexity increases

Engineering Contradiction:
Improveelectrical insulationVSAvoidfabrication process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by depositing the multi-layer dielectric structure into the isolation trench before subsequent contact etching and device fabrication steps. This advance preparation ensures that the protective liner and bulk dielectric are already in place to prevent short circuits during later processing, simplifying the overall workflow despite the additional deposition steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents short circuits and maintains electrical insulation, ensuring reliable microelectronic device performance by creating a robust isolation trench structure that is resistant to material degradation during processing steps.

Implementation Method 1

deposition of a dielectric layer against walls of the trench

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

etching of portions of the deposited dielectric layer

Methodology Applied
Scientific EffectPlasma Etching: Plasma

Data Source

PatentUS9437475B2Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
Publication Date: 2016.09.06 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
  • US9437475B2 patent drawing
  • US9437475B2 patent drawing
  • US9437475B2 patent drawing

AI summary

A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.