SOI CMOS Latch Hardening With Series Transistors Against Soft Errors
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Solution Overview
Problem
CMOS circuits are susceptible to soft errors caused by high-energy particles, leading to transient current fluctuations that can result in data loss and system crashes, with existing techniques to harden these circuits being costly in terms of area, delay, and power consumption.
Innovation Solution
The method involves replacing specific transistors in a latch circuit with hardened series transistors, where two transistors are connected in series with a shared source/drain region, reducing the likelihood of soft errors by blocking conduction paths even if one transistor is activated by a high-energy particle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used in latch circuits, then area and power consumption are minimized, but the circuit is highly susceptible to soft errors from high-energy particles
Solution Approach 1:
The patent divides a single transistor into two series-connected transistors, where each transistor can be independently controlled. This segmentation allows the circuit to block soft errors by preventing simultaneous conduction through both transistors, while maintaining a relatively simple overall structure that integrates well into existing latch circuits
2Reliability
If redundant transistors are added to harden the circuit, then soft error protection is improved, but area overhead and power consumption increase significantly
Solution Approach 1:
The patent merges the hardening function into the existing transistor structure by using series-connected transistors that share common diffusion regions and control signals. This combining approach provides soft error protection without requiring completely separate redundant transistor structures, thereby reducing area overhead compared to traditional redundancy methods
3Reliability
If series-connected hardened transistors are used, then soft error rates are reduced, but switching speed may be affected
Solution Approach 1:
The patent implements dynamic control of the series-connected transistors through complementary clock signals (CLK and CLK_bar). The transistors are switched on and off in a coordinated manner that maintains the hardening effect while enabling fast switching operation. The dynamic signal distribution ensures that at least one transistor in each series pair remains non-conducting to block soft errors, while allowing rapid state transitions when needed
Data Source
AI summary
A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.