Lateral Bipolar Transistor Isolation for SOI Gain
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Solution Overview
Problem
Conventional lateral bipolar transistors formed on SOI substrates face challenges in ensuring sufficient collector current and gain due to the limited contact between emitter and collector diffusion regions and the base diffusion region, leading to degraded emitter efficiency and reduced gain.
Innovation Solution
The design incorporates emitter diffusion regions with isolation insulating films reaching the embedded insulating film layer, and base diffusion regions that are positioned away from the emitter diffusion regions, ensuring electrical connections and forming a structure that allows for sufficient contact between emitter, collector, and base diffusion regions, thereby blocking direct current flow and enhancing injection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the base diffusion region is positioned close to the emitter diffusion region to reduce device area, then device integration density is improved, but emitter efficiency is degraded due to increased direct current flow from emitter to base
Solution Approach 1:
An isolation insulating film is introduced as an intermediary element positioned between the emitter diffusion region and the base diffusion region. This film reaches from the silicon layer surface to the embedded oxide film, creating a physical barrier that blocks direct current flow between emitter and base, thereby maintaining emitter efficiency while allowing compact device布局.
Solution Approach 2:
The isolation insulating film extends vertically into the silicon layer, utilizing the third dimension (depth) to achieve isolation. By reaching down to the embedded oxide film, the film creates an effective barrier without increasing the horizontal footprint of the device, thus maintaining small device area while preventing harmful current flow.
2Speed
If the emitter diffusion region and collector diffusion region are formed to reach the embedded oxide film to reduce junction capacitance, then switching speed is improved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The same diffusion process and isolation structure are used for both MOS transistors (source-drain regions reaching embedded oxide) and bipolar transistors (emitter and collector regions reaching embedded oxide). This multi-functional approach allows both device types to benefit from reduced junction capacitance while using identical fabrication processes, thereby avoiding additional manufacturing complexity.
3Reliability
If the base diffusion region is shaped in a well shape with emitter and collector regions contacting at bottom faces and side faces, then collector current is sufficient, but this structure cannot be implemented in lateral bipolar transistors
Solution Approach 1:
The isolation insulating film extends vertically into the silicon layer to create multiple contact surfaces. The base diffusion region contacts the isolation film at its side face, and also at its bottom face where the isolation film reaches the embedded oxide. This vertical extension creates effective contact areas in both lateral and vertical dimensions, ensuring sufficient collector current for lateral bipolar transistors.
Data Source
AI summary
A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.